f_erase.lst

This example demonstrates how to erase, write, and read the on-chip 640-byte EEPROM Data Memory of t

C51 COMPILER V7.00 Beta 5  F_ERASE                                                         04/19/2002 14:12:10 PAGE 1   


C51 COMPILER V7.00 Beta 5, COMPILATION OF MODULE F_ERASE
OBJECT MODULE PLACED IN f_erase.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE f_erase.c OPTIMIZE(9,SPEED) BROWSE DEBUG OBJECTEXTEND CODE LISTINCLUDE SYMB
                    -OLS TABS(8)

stmt level    source

   1          #include <ADUC812.H>
   1      =1  /*REV.  2.0    11th February 2002
   2      =1    ADuC812  Apps, Analog Devices Inc.*/
   3      =1  
   4      =1  /*  BYTE Register  */
   5      =1  sfr   P0        = 0x80;
   6      =1  sfr   SP        = 0x81;
   7      =1  sfr   DPL       = 0x82;
   8      =1  sfr   DPH       = 0x83;
   9      =1  sfr   DPP       = 0x84;
  10      =1  sfr   PCON      = 0x87;
  11      =1  sfr   TCON      = 0x88;
  12      =1  sfr   TMOD      = 0x89;
  13      =1  sfr   TL0       = 0x8A;
  14      =1  sfr   TL1       = 0x8B;
  15      =1  sfr   TH0       = 0x8C;
  16      =1  sfr   TH1       = 0x8D;
  17      =1  sfr   P1        = 0x90;
  18      =1  sfr   SCON      = 0x98;
  19      =1  sfr   SBUF      = 0x99;
  20      =1  sfr   I2CDAT    = 0x9A;
  21      =1  sfr   I2CADD    = 0x9B;
  22      =1  sfr   P2        = 0xA0;
  23      =1  sfr   IE        = 0xA8;
  24      =1  sfr   IE2       = 0xA9;
  25      =1  sfr   P3        = 0xB0;
  26      =1  sfr   IP        = 0xB8;
  27      =1  sfr   ECON      = 0xB9;
  28      =1  sfr   EDATA1    = 0xBC;
  29      =1  sfr   EDATA2    = 0xBD;
  30      =1  sfr   EDATA3    = 0xBE;
  31      =1  sfr   EDATA4    = 0xBF;
  32      =1  sfr   WDCON     = 0xC0;
  33      =1  sfr   EADRL     = 0xC6;
  34      =1  sfr   T2CON     = 0xC8;
  35      =1  sfr   RCAP2L    = 0xCA;
  36      =1  sfr   RCAP2H    = 0xCB;
  37      =1  sfr   TL2       = 0xCC;
  38      =1  sfr   TH2       = 0xCD;
  39      =1  sfr   PSW       = 0xD0;
  40      =1  sfr   DMAL      = 0xD2;
  41      =1  sfr   DMAH      = 0xD3;
  42      =1  sfr   DMAP      = 0xD4;
  43      =1  sfr   ADCCON2   = 0xD8;
  44      =1  sfr   ADCDATAL  = 0xD9;
  45      =1  sfr   ADCDATAH  = 0xDA;
  46      =1  sfr   PSMCON    = 0xDF;
  47      =1  sfr   ACC       = 0xE0;
  48      =1  sfr   I2CCON    = 0xE8;
  49      =1  sfr   DCON      = 0xE8;
  50      =1  sfr   ADCCON1   = 0xEF;
  51      =1  sfr   B         = 0xF0;
  52      =1  sfr   ADCOFSL   = 0xF1;
  53      =1  sfr   ADCOFSH   = 0xF2;
C51 COMPILER V7.00 Beta 5  F_ERASE                                                         04/19/2002 14:12:10 PAGE 2   

  54      =1  sfr   ADCGAINL  = 0xF3;
  55      =1  sfr   ADCGAINH  = 0xF4;
  56      =1  sfr   ADCCON3   = 0xF5;
  57      =1  sfr   SPIDAT    = 0xF7;
  58      =1  sfr   SPICON    = 0xF8;
  59      =1  sfr   DAC0L     = 0xF9;
  60      =1  sfr   DAC0H     = 0xFA;
  61      =1  sfr   DAC1L     = 0xFB;
  62      =1  sfr   DAC1H     = 0xFC;
  63      =1  sfr   DACCON    = 0xFD;
  64      =1  
  65      =1  /* BIT Register..... */
  66      =1  /* TCON */
  67      =1  sbit  TF1       = 0x8F;
  68      =1  sbit  TR1       = 0x8E;
  69      =1  sbit  TF0       = 0x8D;
  70      =1  sbit  TR0       = 0x8C;
  71      =1  sbit  IE1       = 0x8B;
  72      =1  sbit  IT1       = 0x8A;
  73      =1  sbit  IE0       = 0x89;
  74      =1  sbit  IT0       = 0x88;
  75      =1  /* P1 */
  76      =1  sbit  T2EX      = 0x91;
  77      =1  sbit  T2        = 0x90;
  78      =1  /* SCON */
  79      =1  sbit  SM0       = 0x9F;
  80      =1  sbit  SM1       = 0x9E;
  81      =1  sbit  SM2       = 0x9D;
  82      =1  sbit  REN       = 0x9C;
  83      =1  sbit  TB8       = 0x9B;
  84      =1  sbit  RB8       = 0x9A;
  85      =1  sbit  TI        = 0x99;
  86      =1  sbit  RI        = 0x98;
  87      =1  /* IE */
  88      =1  sbit  EA        = 0xAF;
  89      =1  sbit  EADC      = 0xAE;
  90      =1  sbit  ET2       = 0xAD;
  91      =1  sbit  ES        = 0xAC;
  92      =1  sbit  ET1       = 0xAB;
  93      =1  sbit  EX1       = 0xAA;
  94      =1  sbit  ET0       = 0xA9;
  95      =1  sbit  EX0       = 0xA8;
  96      =1  /* P3 */
  97      =1  sbit  RD        = 0xB7;
  98      =1  sbit  WR        = 0xB6;
  99      =1  sbit  T1        = 0xB5;
 100      =1  sbit  T0        = 0xB4;
 101      =1  sbit  INT1      = 0xB3;
 102      =1  sbit  INT0      = 0xB2;
 103      =1  sbit  TXD       = 0xB1;
 104      =1  sbit  RXD       = 0xB0;
 105      =1  /* IP */
 106      =1  sbit  PSI       = 0xBF;
 107      =1  sbit  PADC      = 0xBE;
 108      =1  sbit  PT2       = 0xBD;
 109      =1  sbit  PS        = 0xBC;
 110      =1  sbit  PT1       = 0xBB;
 111      =1  sbit  PX1       = 0xBA;
 112      =1  sbit  PT0       = 0xB9;
 113      =1  sbit  PX0       = 0xB8;
 114      =1  /* WDCON */
 115      =1  sbit  PRE2      = 0xC7;
C51 COMPILER V7.00 Beta 5  F_ERASE                                                         04/19/2002 14:12:10 PAGE 3   

 116      =1  sbit  PRE1      = 0xC6;
 117      =1  sbit  PRE0      = 0xC5;
 118      =1  sbit  WDR1      = 0xC3;
 119      =1  sbit  WDR2      = 0xC2;
 120      =1  sbit  WDS       = 0xC1;
 121      =1  sbit  WDE       = 0xC0;
 122      =1  /* T2CON */
 123      =1  sbit  TF2       = 0xCF;
 124      =1  sbit  EXF2      = 0xCE;
 125      =1  sbit  RCLK      = 0xCD;
 126      =1  sbit  TCLK      = 0xCC;
 127      =1  sbit  EXEN2       = 0xCB;
 128      =1  sbit  TR2       = 0xCA;
 129      =1  sbit  CNT2      = 0xC9;
 130      =1  sbit  CAP2      = 0xC8;
 131      =1  /* PSW */
 132      =1  sbit  CY        = 0xD7;
 133      =1  sbit  AC        = 0xD6;
 134      =1  sbit  F0        = 0xD5;
 135      =1  sbit  RS1       = 0xD4;
 136      =1  sbit  RS0       = 0xD3;
 137      =1  sbit  OV        = 0xD2;
 138      =1  sbit  F1        = 0xD1;
 139      =1  sbit  P         = 0xD0;
 140      =1  /* ADCCON2 */
 141      =1  sbit  ADCI      = 0xDF;
 142      =1  sbit  DMA       = 0xDE;
 143      =1  sbit  CCONV     = 0xDD;
 144      =1  sbit  SCONV     = 0xDC;
 145      =1  sbit  CS3       = 0xDB;
 146      =1  sbit  CS2       = 0xDA;
 147      =1  sbit  CS1       = 0xD9;
 148      =1  sbit  CS0       = 0xD8;
 149      =1  /* I2CCON */
 150      =1  sbit  MDO       = 0xEF;
 151      =1  sbit  MDE       = 0xEE;
 152      =1  sbit  MCO       = 0xED;
 153      =1  sbit  MDI       = 0xEC;
 154      =1  sbit  I2CM      = 0xEB;
 155      =1  sbit  I2CRS     = 0xEA;
 156      =1  sbit  I2CTX     = 0xE9;
 157      =1  sbit  I2CI      = 0xE8;
 158      =1  /*  DCON  */
 159      =1  sbit D1         = DCON^7;
 160      =1  sbit D1EN       = DCON^6;
 161      =1  sbit D0         = DCON^5;
 162      =1  sbit D0EN       = DCON^3;