epp.vhd

并口的EPP协议

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--*********************************************
ENTITY EPP is
	PORT(
			clk,nDataStrobe,nInit,empty : IN STD_LOGIC;
			DataIn : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			DataOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
			--T1,T2,T3 : OUT STD_LOGIC;
			restart,nwait,rdpulse : OUT STD_LOGIC  
		);
END EPP;
--*********************************************
ARCHITECTURE rtl OF EPP IS
SIGNAL Q1, Q2,Q3,Q4,Q5,rest,read,in_rdpulse,in_nwait: Std_logic;
BEGIN
 --T1<=Q1;
 --T2<=Q2;
 --T3<=Q3;
 rest<=NOT nInit;
 restart<=rest;
 ---------------------------------------------------------------
 rdpulsegenerator:
 BLOCK
 BEGIN
 read<=(NOT nDataStrobe) AND (NOT empty);
 in_rdpulse <= Q1 and not(Q2);
 rdpulse <=in_rdpulse; 
 PROCESS(clk,rest)                                     
  BEGIN
    IF(rest='1')THEN
        Q1 <= '0';
        Q2 <= '0'; 
    ELSIF(clk'EVENT AND clk='1')THEN
        Q1 <= read;
        Q2 <= Q1;   
    END IF;
 END PROCESS;
 END BLOCk rdpulsegenerator;
 -------------------------------------------------------------
 nwaitgenerator:
 BLOCK
 BEGIN
 in_nwait<=(NOT nDataStrobe) AND Q3;
 nwait<=Q5;
 PROCESS(clk,rest)                                     
  BEGIN
    IF(rest='1')THEN
         Q3<='0';
         Q4<='0';
         Q5<='0';
    ELSIF(clk'EVENT AND clk='1')THEN
      Q4<=Q3;
      Q5<=Q4;
      IF(in_rdpulse='1')THEN
         Q3<=(NOT nDataStrobe); 
      ELSIF(nDataStrobe='1')THEN
         Q3<='0';
      END IF;
    END IF;
 END PROCESS;
 END BLOCk nwaitgenerator;
 -------------------------------------------------------------
 datagenerator:
 BLOCK
 BEGIN
 PROCESS(clk,rest)                                     
  BEGIN
    IF(rest='1')THEN
         DataOut<="ZZZZZZZZ";
    ELSIF(clk'EVENT AND clk='1')THEN
      IF(in_nwait='1')THEN
         DataOut<=DataIn;
      ELSE
         DataOut<="ZZZZZZZZ";
      END IF;
    END IF;
 END PROCESS;
 END BLOCk datagenerator;
 --------------------------------------------------------------

 --------------------------------------------------------------
END rtl;