count_16_7.tan.qmsg

使用Vhdl语言编写的FPGA应用程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 24 16:58:36 2005 " "Info: Processing started: Thu Nov 24 16:58:36 2005" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off COUNT_16_7 -c COUNT_16_7 --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off COUNT_16_7 -c COUNT_16_7 --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "CLK1 " "Info: Assuming node CLK1 is an undefined clock" {  } { { "C:/Documents and Settings/郑峥/桌面/复件 ASDF/复件 ASDF/COUNT_16_7.vhd" "" "" { Text "C:/Documents and Settings/郑峥/桌面/复件 ASDF/复件 ASDF/COUNT_16_7.vhd" 5 -1 0 } } { "f:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "f:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK1" } } } }  } 0}  } {  } 0}