etester.fit.summary

来自「使用vhdl语言写的fpga的应用程序」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Fri Dec 02 16:41:14 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : ETESTER
Top-level Entity Name : ETESTER
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 7 / 2,910 ( < 1 % )
Total pins : 18 / 104 ( 17 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )