etester.tan.qmsg

使用vhdl语言写的fpga的应用程序

{ "Info" "ITDB_FULL_TCO_RESULT" "CL EEND Q2 15.338 ns register " "Info: tco from clock CL to destination pin EEND through register Q2 is 15.338 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CL source 10.087 ns + Longest register " "Info: + Longest clock path from clock CL to source register is 10.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CL 1 CLK Pin_57 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_57; Fanout = 3; CLK Node = 'CL'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "" { CL } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.699 ns) + CELL(0.114 ns) 3.288 ns i288~1 2 COMB LC_X15_Y6_N5 1 " "Info: 2: + IC(1.699 ns) + CELL(0.114 ns) = 3.288 ns; Loc. = LC_X15_Y6_N5; Fanout = 1; COMB Node = 'i288~1'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "1.813 ns" { CL i288~1 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.935 ns) 4.679 ns Q1 3 REG LC_X15_Y6_N7 1 " "Info: 3: + IC(0.456 ns) + CELL(0.935 ns) = 4.679 ns; Loc. = LC_X15_Y6_N7; Fanout = 1; REG Node = 'Q1'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "1.391 ns" { i288~1 Q1 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.292 ns) 5.509 ns i292~22 4 COMB LC_X15_Y6_N4 2 " "Info: 4: + IC(0.538 ns) + CELL(0.292 ns) = 5.509 ns; Loc. = LC_X15_Y6_N4; Fanout = 2; COMB Node = 'i292~22'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "0.830 ns" { Q1 i292~22 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.867 ns) + CELL(0.711 ns) 10.087 ns Q2 5 REG LC_X15_Y5_N4 2 " "Info: 5: + IC(3.867 ns) + CELL(0.711 ns) = 10.087 ns; Loc. = LC_X15_Y5_N4; Fanout = 2; REG Node = 'Q2'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "4.578 ns" { i292~22 Q2 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.527 ns 34.97 % " "Info: Total cell delay = 3.527 ns ( 34.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.560 ns 65.03 % " "Info: Total interconnect delay = 6.560 ns ( 65.03 % )" {  } {  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "10.087 ns" { CL i288~1 Q1 i292~22 Q2 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.027 ns + Longest register pin " "Info: + Longest register to pin delay is 5.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q2 1 REG LC_X15_Y5_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y5_N4; Fanout = 2; REG Node = 'Q2'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "" { Q2 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.289 ns) + CELL(0.292 ns) 1.581 ns i~9 2 COMB LC_X16_Y3_N2 1 " "Info: 2: + IC(1.289 ns) + CELL(0.292 ns) = 1.581 ns; Loc. = LC_X16_Y3_N2; Fanout = 1; COMB Node = 'i~9'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "1.581 ns" { Q2 i~9 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.338 ns) + CELL(2.108 ns) 5.027 ns EEND 3 PIN Pin_55 0 " "Info: 3: + IC(1.338 ns) + CELL(2.108 ns) = 5.027 ns; Loc. = Pin_55; Fanout = 0; PIN Node = 'EEND'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "3.446 ns" { i~9 EEND } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns 47.74 % " "Info: Total cell delay = 2.400 ns ( 47.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.627 ns 52.26 % " "Info: Total interconnect delay = 2.627 ns ( 52.26 % )" {  } {  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "5.027 ns" { Q2 i~9 EEND } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "10.087 ns" { CL i288~1 Q1 i292~22 Q2 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "5.027 ns" { Q2 i~9 EEND } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SEL\[1\] DATA\[4\] 15.080 ns Longest " "Info: Longest tpd from source pin SEL\[1\] to destination pin DATA\[4\] is 15.080 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns SEL\[1\] 1 PIN Pin_61 27 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_61; Fanout = 27; PIN Node = 'SEL\[1\]'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "" { SEL[1] } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.171 ns) + CELL(0.590 ns) 7.236 ns i73~660 2 COMB LC_X21_Y2_N1 8 " "Info: 2: + IC(5.171 ns) + CELL(0.590 ns) = 7.236 ns; Loc. = LC_X21_Y2_N1; Fanout = 8; COMB Node = 'i73~660'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "5.761 ns" { SEL[1] i73~660 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.611 ns) + CELL(0.442 ns) 9.289 ns i76~619 3 COMB LC_X23_Y3_N9 1 " "Info: 3: + IC(1.611 ns) + CELL(0.442 ns) = 9.289 ns; Loc. = LC_X23_Y3_N9; Fanout = 1; COMB Node = 'i76~619'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.053 ns" { i73~660 i76~619 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.590 ns) 11.094 ns i76~620 4 COMB LC_X22_Y4_N3 1 " "Info: 4: + IC(1.215 ns) + CELL(0.590 ns) = 11.094 ns; Loc. = LC_X22_Y4_N3; Fanout = 1; COMB Node = 'i76~620'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "1.805 ns" { i76~619 i76~620 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.862 ns) + CELL(2.124 ns) 15.080 ns DATA\[4\] 5 PIN Pin_84 0 " "Info: 5: + IC(1.862 ns) + CELL(2.124 ns) = 15.080 ns; Loc. = Pin_84; Fanout = 0; PIN Node = 'DATA\[4\]'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "3.986 ns" { i76~620 DATA[4] } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.221 ns 34.62 % " "Info: Total cell delay = 5.221 ns ( 34.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.859 ns 65.38 % " "Info: Total interconnect delay = 9.859 ns ( 65.38 % )" {  } {  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "15.080 ns" { SEL[1] i73~660 i76~619 i76~620 DATA[4] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:BZQ_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[15\] SPUL BCLK -5.942 ns register " "Info: th for register lpm_counter:BZQ_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[15\] (data pin = SPUL, clock pin = BCLK) is -5.942 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BCLK destination 2.721 ns + Longest register " "Info: + Longest clock path from clock BCLK to destination register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns BCLK 1 CLK Pin_16 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Pin_16; Fanout = 32; CLK Node = 'BCLK'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "" { BCLK } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns lpm_counter:BZQ_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[15\] 2 REG LC_X22_Y3_N9 3 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X22_Y3_N9; Fanout = 3; REG Node = 'lpm_counter:BZQ_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[15\]'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "1.252 ns" { BCLK lpm_counter:BZQ_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.721 ns" { BCLK lpm_counter:BZQ_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.678 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.678 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns SPUL 1 PIN Pin_59 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_59; Fanout = 1; PIN Node = 'SPUL'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "" { SPUL } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.057 ns) + CELL(0.114 ns) 6.646 ns i314~23 2 COMB LC_X19_Y3_N3 32 " "Info: 2: + IC(5.057 ns) + CELL(0.114 ns) = 6.646 ns; Loc. = LC_X19_Y3_N3; Fanout = 32; COMB Node = 'i314~23'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "5.171 ns" { SPUL i314~23 } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 68 -1 0 } }  } 0} { "Info" "ITD