etester.tan.qmsg

使用vhdl语言写的fpga的应用程序

{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "TCLK " "Info: Assuming node TCLK is an undefined clock" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 5 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "TCLK" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "CL " "Info: Assuming node CL is an undefined clock" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 5 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CL" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "BCLK " "Info: Assuming node BCLK is an undefined clock" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 5 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "BCLK" } } } }  } 0}  } {  } 0}
{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_GATED_CLK" "i288~1 " "Info: Detected gated clock i288~1 as buffer" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 48 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i288~1" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "Q1 " "Info: Detected ripple clock Q1 as buffer" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 52 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Q1" } } } }  } 0} { "Info" "ITDB_GATED_CLK" "i292~22 " "Info: Detected gated clock i292~22 as buffer" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 49 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "i292~22" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "TCLK register register lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[16\] lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[30\] 275.03 MHz Internal " "Info: Clock TCLK Internal fmax is restricted to 275.03 MHz between source register lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[16\] and destination register lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[30\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.451 ns + Longest register register " "Info: + Longest register to register delay is 2.451 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[16\] 1 REG LC_X20_Y3_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y3_N0; Fanout = 4; REG Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[16\]'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.510 ns) + CELL(0.423 ns) 0.933 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[16\]~COUT0 2 COMB LC_X20_Y3_N0 2 " "Info: 2: + IC(0.510 ns) + CELL(0.423 ns) = 0.933 ns; Loc. = LC_X20_Y3_N0; Fanout = 2; COMB Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[16\]~COUT0'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "0.933 ns" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16]~COUT0 } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.011 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[17\]~COUT0 3 COMB LC_X20_Y3_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.011 ns; Loc. = LC_X20_Y3_N1; Fanout = 2; COMB Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[17\]~COUT0'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "0.078 ns" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[17]~COUT0 } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.089 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[18\]~COUT0 4 COMB LC_X20_Y3_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.089 ns; Loc. = LC_X20_Y3_N2; Fanout = 2; COMB Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[18\]~COUT0'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "0.078 ns" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[17]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[18]~COUT0 } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.167 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[19\]~COUT0 5 COMB LC_X20_Y3_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.167 ns; Loc. = LC_X20_Y3_N3; Fanout = 2; COMB Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[19\]~COUT0'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "0.078 ns" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[18]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[19]~COUT0 } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.345 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|counter_cell\[20\]~COUT 6 COMB LC_X20_Y3_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 1.345 ns; Loc. = LC_X20_Y3_N4; Fanout = 6; COMB Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|counter_cell\[20\]~COUT'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "0.178 ns" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[19]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|counter_cell[20]~COUT } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 334 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.553 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|counter_cell\[25\]~COUT 7 COMB LC_X20_Y3_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 1.553 ns; Loc. = LC_X20_Y3_N9; Fanout = 6; COMB Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|counter_cell\[25\]~COUT'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "0.208 ns" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|counter_cell[20]~COUT lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|counter_cell[25]~COUT } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 334 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.451 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[30\] 8 REG LC_X20_Y2_N4 3 " "Info: 8: + IC(0.000 ns) + CELL(0.898 ns) = 2.451 ns; Loc. = LC_X20_Y2_N4; Fanout = 3; REG Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[30\]'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "0.898 ns" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|counter_cell[25]~COUT lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[30] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.941 ns 79.19 % " "Info: Total cell delay = 1.941 ns ( 79.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.510 ns 20.81 % " "Info: Total interconnect delay = 0.510 ns ( 20.81 % )" {  } {  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.451 ns" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[17]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[18]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[19]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|counter_cell[20]~COUT lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|counter_cell[25]~COUT lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[30] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TCLK destination 2.721 ns + Shortest register " "Info: + Shortest clock path from clock TCLK to destination register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns TCLK 1 CLK Pin_17 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Pin_17; Fanout = 35; CLK Node = 'TCLK'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "" { TCLK } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[30\] 2 REG LC_X20_Y2_N4 3 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X20_Y2_N4; Fanout = 3; REG Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[30\]'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "1.252 ns" { TCLK lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[30] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.721 ns" { TCLK lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[30] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TCLK source 2.721 ns - Longest register " "Info: - Longest clock path from clock TCLK to source register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns TCLK 1 CLK Pin_17 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Pin_17; Fanout = 35; CLK Node = 'TCLK'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "" { TCLK } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" "" "" { Text "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/ETESTER.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[16\] 2 REG LC_X20_Y3_N0 4 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X20_Y3_N0; Fanout = 4; REG Node = 'lpm_counter:TSQ_rtl_1\|alt_counter_stratix:wysi_counter\|safe_q\[16\]'" {  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "1.252 ns" { TCLK lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.721 ns" { TCLK lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.721 ns" { TCLK lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[30] } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.721 ns" { TCLK lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.451 ns" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[17]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[18]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[19]~COUT0 lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|counter_cell[20]~COUT lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|counter_cell[25]~COUT lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[30] } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.721 ns" { TCLK lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[30] } "NODE_NAME" } } } { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "2.721 ns" { TCLK lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" "" "" { Report "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER_cmp.qrpt" Compiler "ETESTER" "UNKNOWN" "V1" "C:/Documents and Settings/nj/桌面/等精度频率计/EDA/db/ETESTER.quartus_db" { Floorplan "" "" "" { lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[30] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0}