etester.hier_info

使用vhdl语言写的fpga的应用程序

|ETESTER
BCLK => ~NO_FANOUT~
TCLK => ENA.CLK
TCLK => MA~0.IN1
TCLK => MA~1.IN1
CLR => ENA.ACLR
CLR => Q1.ACLR
CLR => Q2.ACLR
CLR => Q3.ACLR
CL => MA~0.IN0
CL => MA~1.IN0
CL => ENA.DATAIN
SPUL => ~NO_FANOUT~
SEL[0] => ~NO_FANOUT~
SEL[1] => ~NO_FANOUT~
SEL[2] => ~NO_FANOUT~
START <= ENA.DB_MAX_OUTPUT_PORT_TYPE
EEND <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE
DATA[0] <= <GND>
DATA[1] <= <GND>
DATA[2] <= <GND>
DATA[3] <= <GND>
DATA[4] <= <GND>
DATA[5] <= <GND>
DATA[6] <= <GND>
DATA[7] <= <GND>