etester.tan.rpt

使用vhdl语言写的fpga的应用程序

+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C3T144C8        ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                                    ; From                                                             ; To                                                                ;
+------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------+
; Worst-case tsu         ; N/A   ; None          ; 6.432 ns                                       ; SPUL                                                             ; lpm_counter:BZQ_rtl_0|alt_counter_stratix:wysi_counter|safe_q[26] ;
; Worst-case tco         ; N/A   ; None          ; 15.338 ns                                      ; Q2                                                               ; EEND                                                              ;
; Worst-case tpd         ; N/A   ; None          ; 15.080 ns                                      ; SEL[1]                                                           ; DATA[4]                                                           ;
; Worst-case th          ; N/A   ; None          ; -5.942 ns                                      ; SPUL                                                             ; lpm_counter:BZQ_rtl_0|alt_counter_stratix:wysi_counter|safe_q[6]  ;
; Worst-case minimum tco ; N/A   ; None          ; 6.489 ns                                       ; ENA                                                              ; START                                                             ;
; Worst-case minimum tpd ; N/A   ; None          ; 10.888 ns                                      ; SEL[2]                                                           ; DATA[1]                                                           ;
; Clock Setup: 'BCLK'    ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:BZQ_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2] ; lpm_counter:BZQ_rtl_0|alt_counter_stratix:wysi_counter|safe_q[31] ;
; Clock Setup: 'TCLK'    ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[2] ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[31] ;
+------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; TCLK            ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; CL              ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; BCLK            ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'TCLK'                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack                                   ; Actual fmax (period)                                       ; From                                                              ; To                                                                ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+-------------------------------------------------------------------+-------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )             ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[30] ; TCLK       ; TCLK     ; None                        ; None                      ; None                    ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )             ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[4]  ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[16] ; TCLK       ; TCLK     ; None                        ; None                      ; None                    ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )             ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[4]  ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[17] ; TCLK       ; TCLK     ; None                        ; None                      ; None                    ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )             ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[4]  ; lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[18] ; TCLK       ; TCLK     ; None                        ; None                      ; None                    ;