etester.fit.eqn

使用vhdl语言写的fpga的应用程序

A1L86 = SEL[2] # SEL[1] # SEL[0];


--A1L12 is i73~662 at LC_X21_Y2_N5
--operation mode is normal

A1L12 = A1L81 # A1L86 & A1L02 # !A1L86 & C1_safe_q[7];


--A1L22 is i74~615 at LC_X22_Y1_N9
--operation mode is normal

A1L22 = SEL[1] & !SEL[2] & C1_safe_q[30] & SEL[0];


--A1L32 is i74~616 at LC_X20_Y2_N6
--operation mode is normal

A1L32 = SEL[0] & (SEL[1] & C2_safe_q[30] # !SEL[1] & C2_safe_q[14]);


--A1L42 is i74~617 at LC_X21_Y4_N2
--operation mode is normal

A1L42 = !SEL[0] & (SEL[1] & C2_safe_q[22] # !SEL[1] & C2_safe_q[6]);


--A1L52 is i74~618 at LC_X23_Y3_N1
--operation mode is normal

A1L52 = A1L22 # SEL[2] & (A1L32 # A1L42);


--A1L62 is i74~619 at LC_X23_Y3_N5
--operation mode is normal

A1L62 = C1_safe_q[22] & (A1L91 # C1_safe_q[14] & !A1L76) # !C1_safe_q[22] & C1_safe_q[14] & !A1L76;


--A1L72 is i74~620 at LC_X23_Y3_N2
--operation mode is normal

A1L72 = A1L52 # A1L86 & A1L62 # !A1L86 & C1_safe_q[6];


--A1L82 is i75~615 at LC_X22_Y1_N8
--operation mode is normal

A1L82 = SEL[1] & C1_safe_q[29] & !SEL[2] & SEL[0];


--A1L92 is i75~616 at LC_X21_Y4_N5
--operation mode is normal

A1L92 = SEL[0] & (SEL[1] & C2_safe_q[29] # !SEL[1] & C2_safe_q[13]);


--A1L03 is i75~617 at LC_X20_Y5_N2
--operation mode is normal

A1L03 = !SEL[0] & (SEL[1] & C2_safe_q[21] # !SEL[1] & C2_safe_q[5]);


--A1L13 is i75~618 at LC_X21_Y4_N1
--operation mode is normal

A1L13 = A1L82 # SEL[2] & (A1L03 # A1L92);


--A1L23 is i75~619 at LC_X23_Y3_N4
--operation mode is normal

A1L23 = A1L76 & C1_safe_q[21] & A1L91 # !A1L76 & (C1_safe_q[13] # C1_safe_q[21] & A1L91);


--A1L33 is i75~620 at LC_X22_Y4_N2
--operation mode is normal

A1L33 = A1L13 # A1L86 & A1L23 # !A1L86 & C1_safe_q[5];


--A1L43 is i76~615 at LC_X22_Y1_N7
--operation mode is normal

A1L43 = SEL[1] & !SEL[2] & C1_safe_q[28] & SEL[0];


--A1L53 is i76~616 at LC_X21_Y4_N3
--operation mode is normal

A1L53 = SEL[0] & (SEL[1] & C2_safe_q[28] # !SEL[1] & C2_safe_q[12]);


--A1L63 is i76~617 at LC_X20_Y5_N3
--operation mode is normal

A1L63 = !SEL[0] & (SEL[1] & C2_safe_q[20] # !SEL[1] & C2_safe_q[4]);


--A1L73 is i76~618 at LC_X21_Y4_N4
--operation mode is normal

A1L73 = A1L43 # SEL[2] & (A1L63 # A1L53);


--A1L83 is i76~619 at LC_X23_Y3_N9
--operation mode is normal

A1L83 = C1_safe_q[12] & (A1L91 & C1_safe_q[20] # !A1L76) # !C1_safe_q[12] & A1L91 & C1_safe_q[20];


--A1L93 is i76~620 at LC_X22_Y4_N3
--operation mode is normal

A1L93 = A1L73 # A1L86 & A1L83 # !A1L86 & C1_safe_q[4];


--A1L04 is i77~615 at LC_X21_Y3_N6
--operation mode is normal

A1L04 = !SEL[2] & C1_safe_q[27] & SEL[1] & SEL[0];


--A1L14 is i77~616 at LC_X21_Y3_N8
--operation mode is normal

A1L14 = SEL[0] & (SEL[1] & C2_safe_q[27] # !SEL[1] & C2_safe_q[11]);


--A1L24 is i77~617 at LC_X20_Y5_N0
--operation mode is normal

A1L24 = !SEL[0] & (SEL[1] & C2_safe_q[19] # !SEL[1] & C2_safe_q[3]);


--A1L34 is i77~618 at LC_X21_Y3_N2
--operation mode is normal

A1L34 = A1L04 # SEL[2] & (A1L24 # A1L14);


--A1L44 is i77~619 at LC_X23_Y3_N3
--operation mode is normal

A1L44 = A1L76 & C1_safe_q[19] & A1L91 # !A1L76 & (C1_safe_q[11] # C1_safe_q[19] & A1L91);


--A1L54 is i77~620 at LC_X23_Y3_N7
--operation mode is normal

A1L54 = A1L34 # A1L86 & A1L44 # !A1L86 & C1_safe_q[3];


--A1L64 is i78~615 at LC_X21_Y4_N9
--operation mode is normal

A1L64 = SEL[1] & !SEL[2] & C1_safe_q[26] & SEL[0];


--A1L74 is i78~616 at LC_X21_Y4_N6
--operation mode is normal

A1L74 = SEL[0] & (SEL[1] & C2_safe_q[26] # !SEL[1] & C2_safe_q[10]);


--A1L84 is i78~617 at LC_X20_Y5_N1
--operation mode is normal

A1L84 = !SEL[0] & (SEL[1] & C2_safe_q[18] # !SEL[1] & C2_safe_q[2]);


--A1L94 is i78~618 at LC_X21_Y4_N7
--operation mode is normal

A1L94 = A1L64 # SEL[2] & (A1L84 # A1L74);


--A1L05 is i78~619 at LC_X22_Y4_N0
--operation mode is normal

A1L05 = A1L91 & (C1_safe_q[18] # C1_safe_q[10] & !A1L76) # !A1L91 & C1_safe_q[10] & !A1L76;


--A1L15 is i78~620 at LC_X22_Y4_N1
--operation mode is normal

A1L15 = A1L94 # A1L86 & A1L05 # !A1L86 & C1_safe_q[2];


--A1L25 is i79~615 at LC_X21_Y3_N9
--operation mode is normal

A1L25 = !SEL[2] & SEL[1] & C1_safe_q[25] & SEL[0];


--A1L35 is i79~616 at LC_X21_Y3_N5
--operation mode is normal

A1L35 = SEL[0] & (SEL[1] & C2_safe_q[25] # !SEL[1] & C2_safe_q[9]);


--A1L45 is i79~617 at LC_X21_Y3_N7
--operation mode is normal

A1L45 = !SEL[0] & (SEL[1] & C2_safe_q[17] # !SEL[1] & C2_safe_q[1]);


--A1L55 is i79~618 at LC_X21_Y3_N3
--operation mode is normal

A1L55 = A1L25 # SEL[2] & (A1L35 # A1L45);


--A1L65 is i79~619 at LC_X21_Y3_N0
--operation mode is normal

A1L65 = A1L91 & (C1_safe_q[17] # C1_safe_q[9] & !A1L76) # !A1L91 & C1_safe_q[9] & !A1L76;


--A1L75 is i79~620 at LC_X21_Y3_N4
--operation mode is normal

A1L75 = A1L55 # A1L86 & A1L65 # !A1L86 & C1_safe_q[1];


--A1L85 is i80~569 at LC_X21_Y2_N6
--operation mode is normal

A1L85 = SEL[1] & SEL[0] & !SEL[2] & C1_safe_q[24];


--A1L95 is i80~570 at LC_X21_Y2_N8
--operation mode is normal

A1L95 = SEL[0] & (SEL[1] & C2_safe_q[24] # !SEL[1] & C2_safe_q[8]);


--A1L06 is i80~571 at LC_X21_Y2_N7
--operation mode is normal

A1L06 = !SEL[0] & (SEL[1] & C2_safe_q[16] # !SEL[1] & C2_safe_q[0]);


--A1L16 is i80~572 at LC_X21_Y2_N3
--operation mode is normal

A1L16 = A1L85 # SEL[2] & (A1L06 # A1L95);


--A1L26 is i80~573 at LC_X21_Y2_N2
--operation mode is normal

A1L26 = A1L91 & (C1_safe_q[16] # C1_safe_q[8] & !A1L76) # !A1L91 & C1_safe_q[8] & !A1L76;


--A1L36 is i80~574 at LC_X21_Y2_N9
--operation mode is normal

A1L36 = A1L16 # A1L86 & A1L26 # !A1L86 & C1_safe_q[0];


--Q1 is Q1 at LC_X15_Y6_N7
--operation mode is normal

Q1_lut_out = VCC;
Q1 = DFFEA(Q1_lut_out, A1L46, !GLOBAL(CLR), , , , );


--A1L46 is i288~1 at LC_X15_Y6_N5
--operation mode is normal

A1L46 = TCLK $ CL;


--A1L66 is i314~23 at LC_X19_Y3_N3
--operation mode is normal

ENA_qfbk = ENA;
A1L66 = SPUL & ENA_qfbk # !SPUL & Q3 & !Q2;

--ENA is ENA at LC_X19_Y3_N3
--operation mode is normal

ENA_sload_eqn = CL;
ENA = DFFEA(ENA_sload_eqn, GLOBAL(TCLK), !GLOBAL(CLR), , , , );


--A1L56 is i292~22 at LC_X15_Y6_N4
--operation mode is normal

A1L56 = TCLK $ CL # !Q1;


--SEL[0] is SEL[0] at Pin_68
--operation mode is input

SEL[0] = INPUT();


--SEL[1] is SEL[1] at Pin_61
--operation mode is input

SEL[1] = INPUT();


--SEL[2] is SEL[2] at Pin_70
--operation mode is input

SEL[2] = INPUT();


--CL is CL at Pin_57
--operation mode is input

CL = INPUT();


--TCLK is TCLK at Pin_17
--operation mode is input

TCLK = INPUT();


--CLR is CLR at Pin_93
--operation mode is input

CLR = INPUT();


--BCLK is BCLK at Pin_16
--operation mode is input

BCLK = INPUT();


--SPUL is SPUL at Pin_59
--operation mode is input

SPUL = INPUT();


--START is START at Pin_62
--operation mode is output

START = OUTPUT(ENA);


--EEND is EEND at Pin_55
--operation mode is output

EEND = OUTPUT(!A1L96);


--DATA[7] is DATA[7] at Pin_60
--operation mode is output

DATA[7] = OUTPUT(A1L12);


--DATA[6] is DATA[6] at Pin_78
--operation mode is output

DATA[6] = OUTPUT(A1L72);


--DATA[5] is DATA[5] at Pin_79
--operation mode is output

DATA[5] = OUTPUT(A1L33);


--DATA[4] is DATA[4] at Pin_84
--operation mode is output

DATA[4] = OUTPUT(A1L93);


--DATA[3] is DATA[3] at Pin_69
--operation mode is output

DATA[3] = OUTPUT(A1L54);


--DATA[2] is DATA[2] at Pin_82
--operation mode is output

DATA[2] = OUTPUT(A1L15);


--DATA[1] is DATA[1] at Pin_67
--operation mode is output

DATA[1] = OUTPUT(A1L75);


--DATA[0] is DATA[0] at Pin_58
--operation mode is output

DATA[0] = OUTPUT(A1L36);