📄 etester.fit.rpt
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+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.81) ; Number of LABs (Total = 16) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 11 ;
; 1 Clock ; 10 ;
; 1 Clock enable ; 8 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.69) ; Number of LABs (Total = 16) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 9 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.38) ; Number of LABs (Total = 16) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 5 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 4 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 8.75) ; Number of LABs (Total = 16) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 4 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 1 ;
; 18 ; 1 ;
; 19 ; 1 ;
; 20 ; 1 ;
+---------------------------------------------+------------------------------+
+------------------+
; Fitter Messages ;
+------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Sat Dec 03 19:39:06 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off ETESTER -c ETESTER
Info: Selected device EP1C3T144C8 for design ETESTER
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C8 is compatible
Info: No exact pin location assignment(s) for 18 pins of 18 total pins
Info: Pin START not assigned to an exact location on the device
Info: Pin EEND not assigned to an exact location on the device
Info: Pin DATA[7] not assigned to an exact location on the device
Info: Pin DATA[6] not assigned to an exact location on the device
Info: Pin DATA[5] not assigned to an exact location on the device
Info: Pin DATA[4] not assigned to an exact location on the device
Info: Pin DATA[3] not assigned to an exact location on the device
Info: Pin DATA[2] not assigned to an exact location on the device
Info: Pin DATA[1] not assigned to an exact location on the device
Info: Pin DATA[0] not assigned to an exact location on the device
Info: Pin SEL[0] not assigned to an exact location on the device
Info: Pin SEL[1] not assigned to an exact location on the device
Info: Pin SEL[2] not assigned to an exact location on the device
Info: Pin CL not assigned to an exact location on the device
Info: Pin TCLK not assigned to an exact location on the device
Info: Pin CLR not assigned to an exact location on the device
Info: Pin BCLK not assigned to an exact location on the device
Info: Pin SPUL not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency
Info: Performing register packing on non-logic cell registers with location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal TCLK to use Global clock in Pin 17
Info: Destination i288~1 may be non-global or may not use global clock
Info: Destination i292~22 may be non-global or may not use global clock
Info: Automatically promoted signal BCLK to use Global clock in Pin 16
Info: Automatically promoted signal i292~22 to use Global clock
Info: Automatically promoted signal CLR to use Global clock in Pin 93
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP Scan-chain Inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF
Info: Number of I/O pins in group: 15 (unused VREF, 3.30 VCCIO, 5 input, 10 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: Details of I/O bank before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used -- 18 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 24 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: Details of I/O bank after I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 19 total pin(s) used -- 3 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 24 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 3.112 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y5; Fanout = 4; REG Node = 'lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[1]'
Info: 2: + IC(0.461 ns) + CELL(0.575 ns) = 1.036 ns; Loc. = LAB_X20_Y5; Fanout = 2; COMB Node = 'lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[1]~COUT1'
Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.116 ns; Loc. = LAB_X20_Y5; Fanout = 2; COMB Node = 'lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[2]~COUT1'
Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.196 ns; Loc. = LAB_X20_Y5; Fanout = 2; COMB Node = 'lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[3]~COUT1'
Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.276 ns; Loc. = LAB_X20_Y5; Fanout = 2; COMB Node = 'lpm_counter:TSQ_rtl_1|alt_counter_stratix:wysi_counter|safe_q[4]~COUT1'
Info: 6: + IC(0.000 ns) + CELL(0.2⌨️ 快捷键说明
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