count8.vhd

来自「串口通信实验程序」· VHDL 代码 · 共 23 行

--count8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count8 is
  port(clk: in std_logic;
       q:out std_logic_vector(7 downto 0));
end count8;
architecture rtl of count8 is
 signal q_out:std_logic_vector(7 downto 0);
begin
    process(clk)
    begin
      if clk='1' and clk'event then
         if q_out="11111111" then
            q_out<="00000000";
         else
            q_out<=q_out+'1';
         end if;
      end if;
    end process;
  q<=q_out;
end rtl;