count8.tan.rpt

串口通信实验程序

; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5] ; clk        ; clk      ; None                        ; None                      ; 1.547 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[6] ; clk        ; clk      ; None                        ; None                      ; 1.547 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[7] ; clk        ; clk      ; None                        ; None                      ; 1.547 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5] ; clk        ; clk      ; None                        ; None                      ; 1.546 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[6] ; clk        ; clk      ; None                        ; None                      ; 1.546 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[7] ; clk        ; clk      ; None                        ; None                      ; 1.546 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5] ; clk        ; clk      ; None                        ; None                      ; 1.501 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[6] ; clk        ; clk      ; None                        ; None                      ; 1.501 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[7] ; clk        ; clk      ; None                        ; None                      ; 1.501 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; clk        ; clk      ; None                        ; None                      ; 1.406 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[0] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; clk        ; clk      ; None                        ; None                      ; 1.395 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; clk        ; clk      ; None                        ; None                      ; 1.346 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; clk        ; clk      ; None                        ; None                      ; 1.344 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; clk        ; clk      ; None                        ; None                      ; 1.336 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[0] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; clk        ; clk      ; None                        ; None                      ; 1.335 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[7] ; clk        ; clk      ; None                        ; None                      ; 1.277 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[0] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2] ; clk        ; clk      ; None                        ; None                      ; 1.275 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[6] ; clk        ; clk      ; None                        ; None                      ; 1.217 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2] ; clk        ; clk      ; None                        ; None                      ; 1.216 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[0] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; clk        ; clk      ; None                        ; None                      ; 1.215 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[6] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[7] ; clk        ; clk      ; None                        ; None                      ; 1.215 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; clk        ; clk      ; None                        ; None                      ; 0.938 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2] ; clk        ; clk      ; None                        ; None                      ; 0.937 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[7] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[7] ; clk        ; clk      ; None                        ; None                      ; 0.936 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; clk        ; clk      ; None                        ; None                      ; 0.935 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5] ; clk        ; clk      ; None                        ; None                      ; 0.837 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; clk        ; clk      ; None                        ; None                      ; 0.836 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[0] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[0] ; clk        ; clk      ; None                        ; None                      ; 0.835 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[6] ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[6] ; clk        ; clk      ; None                        ; None                      ; 0.835 ns                ;
+-------+------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                               ;
+-------+--------------+------------+-----------------------------------------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                                                      ; To   ; From Clock ;
+-------+--------------+------------+-----------------------------------------------------------+------+------------+
; N/A   ; None         ; 6.642 ns   ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5] ; q[5] ; clk        ;
; N/A   ; None         ; 6.641 ns   ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[0] ; q[0] ; clk        ;
; N/A   ; None         ; 6.641 ns   ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[7] ; q[7] ; clk        ;
; N/A   ; None         ; 6.638 ns   ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[3] ; q[3] ; clk        ;
; N/A   ; None         ; 6.615 ns   ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[6] ; q[6] ; clk        ;
; N/A   ; None         ; 6.607 ns   ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[4] ; q[4] ; clk        ;
; N/A   ; None         ; 6.417 ns   ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2] ; q[2] ; clk        ;
; N/A   ; None         ; 6.245 ns   ; lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[1] ; q[1] ; clk        ;
+-------+--------------+------------+-----------------------------------------------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Thu Jan 12 20:22:48 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off count8 -c count8 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2]" and destination register "lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.607 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y1_N2; Fanout = 4; REG Node = 'lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2]'
            Info: 2: + IC(0.398 ns) + CELL(0.443 ns) = 0.841 ns; Loc. = LC_X52_Y1_N2; Fanout = 2; COMB Node = 'lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|counter_cella2~COUT'
            Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.899 ns; Loc. = LC_X52_Y1_N3; Fanout = 2; COMB Node = 'lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|counter_cella3~COUT'
            Info: 4: + IC(0.000 ns) + CELL(0.130 ns) = 1.029 ns; Loc. = LC_X52_Y1_N4; Fanout = 3; COMB Node = 'lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|counter_cella4~COUT'
            Info: 5: + IC(0.000 ns) + CELL(0.578 ns) = 1.607 ns; Loc. = LC_X52_Y1_N5; Fanout = 4; REG Node = 'lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5]'
            Info: Total cell delay = 1.209 ns ( 75.23 % )
            Info: Total interconnect delay = 0.398 ns ( 24.77 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.917 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X52_Y1_N5; Fanout = 4; REG Node = 'lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5]'
                Info: Total cell delay = 1.267 ns ( 43.44 % )
                Info: Total interconnect delay = 1.650 ns ( 56.56 % )
            Info: - Longest clock path from clock "clk" to source register is 2.917 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X52_Y1_N2; Fanout = 4; REG Node = 'lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[2]'
                Info: Total cell delay = 1.267 ns ( 43.44 % )
                Info: Total interconnect delay = 1.650 ns ( 56.56 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clk" to destination pin "q[5]" through register "lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5]" is 6.642 ns
    Info: + Longest clock path from clock "clk" to source register is 2.917 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.650 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X52_Y1_N5; Fanout = 4; REG Node = 'lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5]'
        Info: Total cell delay = 1.267 ns ( 43.44 % )
        Info: Total interconnect delay = 1.650 ns ( 56.56 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.569 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y1_N5; Fanout = 4; REG Node = 'lpm_counter:q_out_rtl_0|cntr_it6:auto_generated|safe_q[5]'
        Info: 2: + IC(1.165 ns) + CELL(2.404 ns) = 3.569 ns; Loc. = PIN_AA2; Fanout = 0; PIN Node = 'q[5]'
        Info: Total cell delay = 2.404 ns ( 67.36 % )
        Info: Total interconnect delay = 1.165 ns ( 32.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jan 12 20:22:49 2006
    Info: Elapsed time: 00:00:01