count26.fit.rpt

串口通信实验程序

; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Error detection CRC                          ; Off                      ;
; Reserve Data[0] pin after configuration      ; As input tri-stated      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/20036016_5/count26.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/20036016_5/count26.pin.


+-----------------------------------------------------------------+
; Fitter Resource Usage Summary                                   ;
+-----------------------------------------+-----------------------+
; Resource                                ; Usage                 ;
+-----------------------------------------+-----------------------+
; Total logic elements                    ; 14 / 10,570 ( < 1 % ) ;
;     -- Combinational with no register   ; 5                     ;
;     -- Register only                    ; 0                     ;
;     -- Combinational with a register    ; 9                     ;
;                                         ;                       ;
; Logic element usage by number of inputs ;                       ;
;     -- 4 input functions                ; 4                     ;
;     -- 3 input functions                ; 0                     ;
;     -- 2 input functions                ; 7                     ;
;     -- 1 input functions                ; 3                     ;
;     -- 0 input functions                ; 0                     ;
;                                         ;                       ;
; Logic elements by mode                  ;                       ;
;     -- arithmetic mode                  ; 6                     ;
;     -- qfbk mode                        ; 0                     ;
;     -- register cascade mode            ; 0                     ;
;     -- synchronous clear/load mode      ; 8                     ;
;     -- asynchronous clear/load mode     ; 0                     ;
;                                         ;                       ;
; Total LABs                              ; 2 / 1,057 ( < 1 % )   ;
; Logic elements in carry chains          ; 8                     ;
; User inserted logic elements            ; 0                     ;
; Virtual pins                            ; 0                     ;
; I/O pins                                ; 2 / 336 ( < 1 % )     ;
;     -- Clock pins                       ; 1 / 16 ( 6 % )        ;
; Global signals                          ; 1                     ;
; M512s                                   ; 0 / 94 ( 0 % )        ;
; M4Ks                                    ; 0 / 60 ( 0 % )        ;
; M-RAMs                                  ; 0 / 1 ( 0 % )         ;
; Total memory bits                       ; 0 / 920,448 ( 0 % )   ;
; Total RAM block bits                    ; 0 / 920,448 ( 0 % )   ;
; DSP block 9-bit elements                ; 0 / 48 ( 0 % )        ;
; Global clocks                           ; 1 / 16 ( 6 % )        ;
; Regional clocks                         ; 0 / 16 ( 0 % )        ;
; Fast regional clocks                    ; 0 / 8 ( 0 % )         ;
; SERDES transmitters                     ; 0 / 44 ( 0 % )        ;
; SERDES receivers                        ; 0 / 44 ( 0 % )        ;
; Maximum fan-out node                    ; clkin                 ;
; Maximum fan-out                         ; 9                     ;
; Total fan-out                           ; 55                    ;
; Average fan-out                         ; 3.24                  ;
+-----------------------------------------+-----------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                  ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clkin ; L2    ; 5        ; 53           ; 19           ; 3           ; 9                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                       ;
+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ;
+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+
; clkout ; W21   ; 1        ; 0            ; 2            ; 2           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; Fitter               ;
+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+


+----------------------------------------------------------+
; I/O Bank Usage                                           ;
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage          ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
; 1        ; 1 / 29 ( 3 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 30 ( 0 % ) ; 3.3V          ; --           ;
; 3        ; 0 / 51 ( 0 % ) ; 3.3V          ; --           ;
; 4        ; 1 / 52 ( 1 % ) ; 3.3V          ; --           ;
; 5        ; 1 / 29 ( 3 % ) ; 3.3V          ; --           ;
; 6        ; 0 / 29 ( 0 % ) ; 3.3V          ; --           ;
; 7        ; 0 / 52 ( 0 % ) ; 3.3V          ; --           ;
; 8        ; 0 / 51 ( 0 % ) ; 3.3V          ; --           ;