count26.tan.rpt

串口通信实验程序

; N/A   ; 390.47 MHz ( period = 2.561 ns )               ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[1] ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[0] ; clkin      ; clkin    ; None                        ; None                      ; 2.395 ns                ;
; N/A   ; 399.36 MHz ( period = 2.504 ns )               ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[1] ; lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[3]  ; clkin      ; clkin    ; None                        ; None                      ; 2.338 ns                ;
; N/A   ; 399.36 MHz ( period = 2.504 ns )               ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[1] ; lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[2]  ; clkin      ; clkin    ; None                        ; None                      ; 2.338 ns                ;
; N/A   ; 399.36 MHz ( period = 2.504 ns )               ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[1] ; lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[1]  ; clkin      ; clkin    ; None                        ; None                      ; 2.338 ns                ;
; N/A   ; 399.36 MHz ( period = 2.504 ns )               ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[1] ; lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[0]  ; clkin      ; clkin    ; None                        ; None                      ; 2.338 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[3]  ; clkout~reg0                                               ; clkin      ; clkin    ; None                        ; None                      ; 1.982 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[2] ; clkout~reg0                                               ; clkin      ; clkin    ; None                        ; None                      ; 1.956 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[0]  ; clkout~reg0                                               ; clkin      ; clkin    ; None                        ; None                      ; 1.899 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[1]  ; clkout~reg0                                               ; clkin      ; clkin    ; None                        ; None                      ; 1.784 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[2]  ; clkout~reg0                                               ; clkin      ; clkin    ; None                        ; None                      ; 1.777 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[3] ; clkout~reg0                                               ; clkin      ; clkin    ; None                        ; None                      ; 1.770 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[0] ; clkout~reg0                                               ; clkin      ; clkin    ; None                        ; None                      ; 1.275 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[1] ; clkout~reg0                                               ; clkin      ; clkin    ; None                        ; None                      ; 1.170 ns                ;
+-------+------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 6.269 ns   ; clkout~reg0 ; clkout ; clkin      ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Thu Jan 12 19:51:50 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off count26 -c count26 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkin" is an undefined clock
Info: Clock "clkin" has Internal fmax of 296.47 MHz between source register "lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[3]" and destination register "lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[3]" (period= 3.373 ns)
    Info: + Longest register to register delay is 3.207 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N8; Fanout = 4; REG Node = 'lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[3]'
        Info: 2: + IC(0.450 ns) + CELL(0.366 ns) = 0.816 ns; Loc. = LC_X1_Y2_N1; Fanout = 1; COMB Node = 'process0~34'
        Info: 3: + IC(0.321 ns) + CELL(0.280 ns) = 1.417 ns; Loc. = LC_X1_Y2_N9; Fanout = 2; COMB Node = 'process0~0'
        Info: 4: + IC(0.336 ns) + CELL(0.280 ns) = 2.033 ns; Loc. = LC_X1_Y2_N0; Fanout = 8; COMB Node = 'bcd1[3]~12'
        Info: 5: + IC(0.469 ns) + CELL(0.705 ns) = 3.207 ns; Loc. = LC_X2_Y2_N3; Fanout = 2; REG Node = 'lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[3]'
        Info: Total cell delay = 1.631 ns ( 50.86 % )
        Info: Total interconnect delay = 1.576 ns ( 49.14 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clkin" to destination register is 2.942 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clkin'
            Info: 2: + IC(1.675 ns) + CELL(0.542 ns) = 2.942 ns; Loc. = LC_X2_Y2_N3; Fanout = 2; REG Node = 'lpm_counter:bcd10_rtl_1|cntr_e08:auto_generated|safe_q[3]'
            Info: Total cell delay = 1.267 ns ( 43.07 % )
            Info: Total interconnect delay = 1.675 ns ( 56.93 % )
        Info: - Longest clock path from clock "clkin" to source register is 2.942 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clkin'
            Info: 2: + IC(1.675 ns) + CELL(0.542 ns) = 2.942 ns; Loc. = LC_X1_Y2_N8; Fanout = 4; REG Node = 'lpm_counter:bcd1_rtl_0|cntr_2c7:auto_generated|safe_q[3]'
            Info: Total cell delay = 1.267 ns ( 43.07 % )
            Info: Total interconnect delay = 1.675 ns ( 56.93 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clkin" to destination pin "clkout" through register "clkout~reg0" is 6.269 ns
    Info: + Longest clock path from clock "clkin" to source register is 2.942 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clkin'
        Info: 2: + IC(1.675 ns) + CELL(0.542 ns) = 2.942 ns; Loc. = LC_X1_Y2_N4; Fanout = 1; REG Node = 'clkout~reg0'
        Info: Total cell delay = 1.267 ns ( 43.07 % )
        Info: Total interconnect delay = 1.675 ns ( 56.93 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.171 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N4; Fanout = 1; REG Node = 'clkout~reg0'
        Info: 2: + IC(0.795 ns) + CELL(2.376 ns) = 3.171 ns; Loc. = PIN_W21; Fanout = 0; PIN Node = 'clkout'
        Info: Total cell delay = 2.376 ns ( 74.93 % )
        Info: Total interconnect delay = 0.795 ns ( 25.07 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jan 12 19:51:51 2006
    Info: Elapsed time: 00:00:02