📄 total.tan.qmsg

📁 串口通信实验程序
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_1Hz register register count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 125.0 MHz Internal " "Info: Clock \"clk_1Hz\" Internal fmax is restricted to 125.0 MHz between source register \"count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination register \"count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest register register " "Info: + Longest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_A5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A5; Fanout = 4; REG Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT 2 COMB LC1_A5 2 " "Info: 2: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = LC1_A5; Fanout = 2; COMB Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "1.200 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 1.500 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT 3 COMB LC2_A5 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 1.500 ns; Loc. = LC2_A5; Fanout = 2; COMB Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "0.300 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 1.800 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT 4 COMB LC3_A5 3 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_A5; Fanout = 3; COMB Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "0.300 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 2.100 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~COUT 5 COMB LC4_A5 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 2.100 ns; Loc. = LC4_A5; Fanout = 2; COMB Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~COUT'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "0.300 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 2.400 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]~COUT 6 COMB LC5_A5 3 " "Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 2.400 ns; Loc. = LC5_A5; Fanout = 3; COMB Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]~COUT'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "0.300 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 2.700 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\]~COUT 7 COMB LC6_A5 3 " "Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 2.700 ns; Loc. = LC6_A5; Fanout = 3; COMB Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\]~COUT'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "0.300 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.000 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[6\]~COUT 8 COMB LC7_A5 1 " "Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 3.000 ns; Loc. = LC7_A5; Fanout = 1; COMB Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[6\]~COUT'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "0.300 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 3.700 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 9 REG LC8_A5 2 " "Info: 9: + IC(0.000 ns) + CELL(0.700 ns) = 3.700 ns; Loc. = LC8_A5; Fanout = 2; REG Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "0.700 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 100.00 % " "Info: Total cell delay = 3.700 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "3.700 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1Hz destination 11.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_1Hz\" to destination register is 11.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk_1Hz 1 CLK PIN_26 22 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_26; Fanout = 22; CLK Node = 'clk_1Hz'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { clk_1Hz } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 240 -16 152 256 "clk_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.700 ns) + CELL(0.000 ns) 11.200 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC8_A5 2 " "Info: 2: + IC(7.700 ns) + CELL(0.000 ns) = 11.200 ns; Loc. = LC8_A5; Fanout = 2; REG Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "7.700 ns" { clk_1Hz count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 31.25 % " "Info: Total cell delay = 3.500 ns ( 31.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.700 ns 68.75 % " "Info: Total interconnect delay = 7.700 ns ( 68.75 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "11.200 ns" { clk_1Hz count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.200 ns" { clk_1Hz clk_1Hz~out count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 7.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1Hz source 11.200 ns - Longest register " "Info: - Longest clock path from clock \"clk_1Hz\" to source register is 11.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk_1Hz 1 CLK PIN_26 22 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_26; Fanout = 22; CLK Node = 'clk_1Hz'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { clk_1Hz } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 240 -16 152 256 "clk_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.700 ns) + CELL(0.000 ns) 11.200 ns count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_A5 4 " "Info: 2: + IC(7.700 ns) + CELL(0.000 ns) = 11.200 ns; Loc. = LC1_A5; Fanout = 4; REG Node = 'count8:inst1\|lpm_counter:q_out_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "7.700 ns" { clk_1Hz count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 31.25 % " "Info: Total cell delay = 3.500 ns ( 31.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.700 ns 68.75 % " "Info: Total interconnect delay = 7.700 ns ( 68.75 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "11.200 ns" { clk_1Hz count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.200 ns" { clk_1Hz clk_1Hz~out count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 7.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "11.200 ns" { clk_1Hz count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.200 ns" { clk_1Hz clk_1Hz~out count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 7.700ns } { 0.000ns 3.500ns 0.000ns } } } { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "11.200 ns" { clk_1Hz count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.200 ns" { clk_1Hz clk_1Hz~out count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 7.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "3.700 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.700ns } } } { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "11.200 ns" { clk_1Hz count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.200 ns" { clk_1Hz clk_1Hz~out count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 7.700ns } { 0.000ns 3.500ns 0.000ns } } } { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "11.200 ns" { clk_1Hz count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.200 ns" { clk_1Hz clk_1Hz~out count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 7.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { count8:inst1|lpm_counter:q_out_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } {  } {  } } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sci:inst2\|Data_out\[1\] clk_1Hz clk_1MHz 6.200 ns register " "Info: tsu for register \"sci:inst2\|Data_out\[1\]\" (data pin = \"clk_1Hz\", clock pin = \"clk_1MHz\") is 6.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.000 ns + Longest pin register " "Info: + Longest pin to register delay is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk_1Hz 1 CLK PIN_26 22 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_26; Fanout = 22; CLK Node = 'clk_1Hz'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { clk_1Hz } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 240 -16 152 256 "clk_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.600 ns) + CELL(2.300 ns) 12.400 ns sci:inst2\|Data_out\[0\]~15 2 COMB LC1_F8 8 " "Info: 2: + IC(6.600 ns) + CELL(2.300 ns) = 12.400 ns; Loc. = LC1_F8; Fanout = 8; COMB Node = 'sci:inst2\|Data_out\[0\]~15'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "8.900 ns" { clk_1Hz sci:inst2|Data_out[0]~15 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.200 ns) 16.000 ns sci:inst2\|Data_out\[1\] 3 REG LC2_F10 1 " "Info: 3: + IC(2.400 ns) + CELL(1.200 ns) = 16.000 ns; Loc. = LC2_F10; Fanout = 1; REG Node = 'sci:inst2\|Data_out\[1\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "3.600 ns" { sci:inst2|Data_out[0]~15 sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 43.75 % " "Info: Total cell delay = 7.000 ns ( 43.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.000 ns 56.25 % " "Info: Total interconnect delay = 9.000 ns ( 56.25 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "16.000 ns" { clk_1Hz sci:inst2|Data_out[0]~15 sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.000 ns" { clk_1Hz clk_1Hz~out sci:inst2|Data_out[0]~15 sci:inst2|Data_out[1] } { 0.000ns 0.000ns 6.600ns 2.400ns } { 0.000ns 3.500ns 2.300ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz destination 12.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_1MHz\" to destination register is 12.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk_1MHz 1 CLK PIN_55 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk_1MHz'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 88 0 168 104 "clk_1MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns count26:inst\|clkout 2 REG LC1_E7 40 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_E7; Fanout = 40; REG Node = 'count26:inst\|clkout'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "3.600 ns" { clk_1MHz count26:inst|clkout } "NODE_NAME" } "" } } { "count26.vhd" "" { Text "E:/chairang/k5/count26.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.900 ns) + CELL(0.000 ns) 12.300 ns sci:inst2\|Data_out\[1\] 3 REG LC2_F10 1 " "Info: 3: + IC(5.900 ns) + CELL(0.000 ns) = 12.300 ns; Loc. = LC2_F10; Fanout = 1; REG Node = 'sci:inst2\|Data_out\[1\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "5.900 ns" { count26:inst|clkout sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 31.71 % " "Info: Total cell delay = 3.900 ns ( 31.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.400 ns 68.29 % " "Info: Total interconnect delay = 8.400 ns ( 68.29 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|Data_out[1] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "16.000 ns" { clk_1Hz sci:inst2|Data_out[0]~15 sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.000 ns" { clk_1Hz clk_1Hz~out sci:inst2|Data_out[0]~15 sci:inst2|Data_out[1] } { 0.000ns 0.000ns 6.600ns 2.400ns } { 0.000ns 3.500ns 2.300ns 1.200ns } } } { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|Data_out[1] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_1MHz TXD sci:inst2\|scir\[3\] 41.600 ns register " "Info: tco from clock \"clk_1MHz\" to destination pin \"TXD\" through register \"sci:inst2\|scir\[3\]\" is 41.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz source 12.300 ns + Longest register " "Info: + Longest clock path from clock \"clk_1MHz\" to source register is 12.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk_1MHz 1 CLK PIN_55 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk_1MHz'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 88 0 168 104 "clk_1MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns count26:inst\|clkout 2 REG LC1_E7 40 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_E7; Fanout = 40; REG Node = 'count26:inst\|clkout'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "3.600 ns" { clk_1MHz count26:inst|clkout } "NODE_NAME" } "" } } { "count26.vhd" "" { Text "E:/chairang/k5/count26.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.900 ns) + CELL(0.000 ns) 12.300 ns sci:inst2\|scir\[3\] 3 REG LC8_F13 7 " "Info: 3: + IC(5.900 ns) + CELL(0.000 ns) = 12.300 ns; Loc. = LC8_F13; Fanout = 7; REG Node = 'sci:inst2\|scir\[3\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "5.900 ns" { count26:inst|clkout sci:inst2|scir[3] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 31.71 % " "Info: Total cell delay = 3.900 ns ( 31.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.400 ns 68.29 % " "Info: Total interconnect delay = 8.400 ns ( 68.29 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|scir[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|scir[3] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.200 ns + Longest register pin " "Info: + Longest register to pin delay is 28.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sci:inst2\|scir\[3\] 1 REG LC8_F13 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_F13; Fanout = 7; REG Node = 'sci:inst2\|scir\[3\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { sci:inst2|scir[3] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(2.300 ns) 6.800 ns sci:inst2\|Txd~130 2 COMB LC7_A4 1 " "Info: 2: + IC(4.500 ns) + CELL(2.300 ns) = 6.800 ns; Loc. = LC7_A4; Fanout = 1; COMB Node = 'sci:inst2\|Txd~130'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "6.800 ns" { sci:inst2|scir[3] sci:inst2|Txd~130 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 9.700 ns sci:inst2\|Txd~131 3 COMB LC1_A4 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 9.700 ns; Loc. = LC1_A4; Fanout = 1; COMB Node = 'sci:inst2\|Txd~131'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "2.900 ns" { sci:inst2|Txd~130 sci:inst2|Txd~131 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 14.200 ns sci:inst2\|Txd~132 4 COMB LC2_A6 1 " "Info: 4: + IC(2.200 ns) + CELL(2.300 ns) = 14.200 ns; Loc. = LC2_A6; Fanout = 1; COMB Node = 'sci:inst2\|Txd~132'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "4.500 ns" { sci:inst2|Txd~131 sci:inst2|Txd~132 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.800 ns) 20.300 ns sci:inst2\|Txd~133 5 COMB LC3_F20 1 " "Info: 5: + IC(4.300 ns) + CELL(1.800 ns) = 20.300 ns; Loc. = LC3_F20; Fanout = 1; COMB Node = 'sci:inst2\|Txd~133'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "6.100 ns" { sci:inst2|Txd~132 sci:inst2|Txd~133 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(5.100 ns) 28.200 ns TXD 6 PIN PIN_19 0 " "Info: 6: + IC(2.800 ns) + CELL(5.100 ns) = 28.200 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'TXD'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "7.900 ns" { sci:inst2|Txd~133 TXD } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 64 648 824 80 "TXD" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.800 ns 48.94 % " "Info: Total cell delay = 13.800 ns ( 48.94 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.400 ns 51.06 % " "Info: Total interconnect delay = 14.400 ns ( 51.06 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "28.200 ns" { sci:inst2|scir[3] sci:inst2|Txd~130 sci:inst2|Txd~131 sci:inst2|Txd~132 sci:inst2|Txd~133 TXD } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "28.200 ns" { sci:inst2|scir[3] sci:inst2|Txd~130 sci:inst2|Txd~131 sci:inst2|Txd~132 sci:inst2|Txd~133 TXD } { 0.000ns 4.500ns 0.600ns 2.200ns 4.300ns 2.800ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.800ns 5.100ns } } }  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|scir[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|scir[3] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "28.200 ns" { sci:inst2|scir[3] sci:inst2|Txd~130 sci:inst2|Txd~131 sci:inst2|Txd~132 sci:inst2|Txd~133 TXD } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "28.200 ns" { sci:inst2|scir[3] sci:inst2|Txd~130 sci:inst2|Txd~131 sci:inst2|Txd~132 sci:inst2|Txd~133 TXD } { 0.000ns 4.500ns 0.600ns 2.200ns 4.300ns 2.800ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.800ns 5.100ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sci:inst2\|scir\[4\] RXD clk_1MHz 8.200 ns register " "Info: th for register \"sci:inst2\|scir\[4\]\" (data pin = \"RXD\", clock pin = \"clk_1MHz\") is 8.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz destination 12.300 ns + Longest register " "Info: + Longest clock path from clock \"clk_1MHz\" to destination register is 12.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk_1MHz 1 CLK PIN_55 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk_1MHz'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 88 0 168 104 "clk_1MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns count26:inst\|clkout 2 REG LC1_E7 40 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_E7; Fanout = 40; REG Node = 'count26:inst\|clkout'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "3.600 ns" { clk_1MHz count26:inst|clkout } "NODE_NAME" } "" } } { "count26.vhd" "" { Text "E:/chairang/k5/count26.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.900 ns) + CELL(0.000 ns) 12.300 ns sci:inst2\|scir\[4\] 3 REG LC4_F13 5 " "Info: 3: + IC(5.900 ns) + CELL(0.000 ns) = 12.300 ns; Loc. = LC4_F13; Fanout = 5; REG Node = 'sci:inst2\|scir\[4\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "5.900 ns" { count26:inst|clkout sci:inst2|scir[4] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 31.71 % " "Info: Total cell delay = 3.900 ns ( 31.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.400 ns 68.29 % " "Info: Total interconnect delay = 8.400 ns ( 68.29 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|scir[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|scir[4] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns RXD 1 PIN PIN_56 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_56; Fanout = 5; PIN Node = 'RXD'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { RXD } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 176 0 168 192 "RXD" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.200 ns) 5.700 ns sci:inst2\|scir\[4\] 2 REG LC4_F13 5 " "Info: 2: + IC(1.700 ns) + CELL(1.200 ns) = 5.700 ns; Loc. = LC4_F13; Fanout = 5; REG Node = 'sci:inst2\|scir\[4\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "2.900 ns" { RXD sci:inst2|scir[4] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 70.18 % " "Info: Total cell delay = 4.000 ns ( 70.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 29.82 % " "Info: Total interconnect delay = 1.700 ns ( 29.82 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "5.700 ns" { RXD sci:inst2|scir[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.700 ns" { RXD RXD~out sci:inst2|scir[4] } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.200ns } } }  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|scir[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|scir[4] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "5.700 ns" { RXD sci:inst2|scir[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.700 ns" { RXD RXD~out sci:inst2|scir[4] } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.200ns } } }  } 0}
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