total.tan.qmsg

串口通信实验程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_1MHz " "Info: Assuming node \"clk_1MHz\" is an undefined clock" {  } { { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 88 0 168 104 "clk_1MHz" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_1MHz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_1Hz " "Info: Assuming node \"clk_1Hz\" is an undefined clock" {  } { { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 240 -16 152 256 "clk_1Hz" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_1Hz" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "count26:inst\|clkout " "Info: Detected ripple clock \"count26:inst\|clkout\" as buffer" {  } { { "count26.vhd" "" { Text "E:/chairang/k5/count26.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "count26:inst\|clkout" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_1MHz register sci:inst2\|scir\[1\] register sci:inst2\|Data_out\[6\] 54.05 MHz 18.5 ns Internal " "Info: Clock \"clk_1MHz\" has Internal fmax of 54.05 MHz between source register \"sci:inst2\|scir\[1\]\" and destination register \"sci:inst2\|Data_out\[6\]\" (period= 18.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.900 ns + Longest register register " "Info: + Longest register to register delay is 14.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sci:inst2\|scir\[1\] 1 REG LC1_F14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F14; Fanout = 4; REG Node = 'sci:inst2\|scir\[1\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { sci:inst2|scir[1] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 4.000 ns sci:inst2\|process0~21 2 COMB LC6_F13 2 " "Info: 2: + IC(2.200 ns) + CELL(1.800 ns) = 4.000 ns; Loc. = LC6_F13; Fanout = 2; COMB Node = 'sci:inst2\|process0~21'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "4.000 ns" { sci:inst2|scir[1] sci:inst2|process0~21 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 6.900 ns sci:inst2\|process0~22 3 COMB LC1_F13 3 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 6.900 ns; Loc. = LC1_F13; Fanout = 3; COMB Node = 'sci:inst2\|process0~22'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "2.900 ns" { sci:inst2|process0~21 sci:inst2|process0~22 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.800 ns) 11.300 ns sci:inst2\|Data_out\[0\]~15 4 COMB LC1_F8 8 " "Info: 4: + IC(2.600 ns) + CELL(1.800 ns) = 11.300 ns; Loc. = LC1_F8; Fanout = 8; COMB Node = 'sci:inst2\|Data_out\[0\]~15'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "4.400 ns" { sci:inst2|process0~22 sci:inst2|Data_out[0]~15 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.200 ns) 14.900 ns sci:inst2\|Data_out\[6\] 5 REG LC1_F9 1 " "Info: 5: + IC(2.400 ns) + CELL(1.200 ns) = 14.900 ns; Loc. = LC1_F9; Fanout = 1; REG Node = 'sci:inst2\|Data_out\[6\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "3.600 ns" { sci:inst2|Data_out[0]~15 sci:inst2|Data_out[6] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.100 ns 47.65 % " "Info: Total cell delay = 7.100 ns ( 47.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.800 ns 52.35 % " "Info: Total interconnect delay = 7.800 ns ( 52.35 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "14.900 ns" { sci:inst2|scir[1] sci:inst2|process0~21 sci:inst2|process0~22 sci:inst2|Data_out[0]~15 sci:inst2|Data_out[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.900 ns" { sci:inst2|scir[1] sci:inst2|process0~21 sci:inst2|process0~22 sci:inst2|Data_out[0]~15 sci:inst2|Data_out[6] } { 0.000ns 2.200ns 0.600ns 2.600ns 2.400ns } { 0.000ns 1.800ns 2.300ns 1.800ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz destination 12.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_1MHz\" to destination register is 12.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk_1MHz 1 CLK PIN_55 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk_1MHz'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 88 0 168 104 "clk_1MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns count26:inst\|clkout 2 REG LC1_E7 40 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_E7; Fanout = 40; REG Node = 'count26:inst\|clkout'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "3.600 ns" { clk_1MHz count26:inst|clkout } "NODE_NAME" } "" } } { "count26.vhd" "" { Text "E:/chairang/k5/count26.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.900 ns) + CELL(0.000 ns) 12.300 ns sci:inst2\|Data_out\[6\] 3 REG LC1_F9 1 " "Info: 3: + IC(5.900 ns) + CELL(0.000 ns) = 12.300 ns; Loc. = LC1_F9; Fanout = 1; REG Node = 'sci:inst2\|Data_out\[6\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "5.900 ns" { count26:inst|clkout sci:inst2|Data_out[6] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 31.71 % " "Info: Total cell delay = 3.900 ns ( 31.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.400 ns 68.29 % " "Info: Total interconnect delay = 8.400 ns ( 68.29 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|Data_out[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|Data_out[6] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz source 12.300 ns - Longest register " "Info: - Longest clock path from clock \"clk_1MHz\" to source register is 12.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk_1MHz 1 CLK PIN_55 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk_1MHz'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 88 0 168 104 "clk_1MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns count26:inst\|clkout 2 REG LC1_E7 40 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_E7; Fanout = 40; REG Node = 'count26:inst\|clkout'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "3.600 ns" { clk_1MHz count26:inst|clkout } "NODE_NAME" } "" } } { "count26.vhd" "" { Text "E:/chairang/k5/count26.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.900 ns) + CELL(0.000 ns) 12.300 ns sci:inst2\|scir\[1\] 3 REG LC1_F14 4 " "Info: 3: + IC(5.900 ns) + CELL(0.000 ns) = 12.300 ns; Loc. = LC1_F14; Fanout = 4; REG Node = 'sci:inst2\|scir\[1\]'" {  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "5.900 ns" { count26:inst|clkout sci:inst2|scir[1] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 31.71 % " "Info: Total cell delay = 3.900 ns ( 31.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.400 ns 68.29 % " "Info: Total interconnect delay = 8.400 ns ( 68.29 % )" {  } {  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|scir[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|scir[1] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|Data_out[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|Data_out[6] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|scir[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|scir[1] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 9 -1 0 } }  } 0}  } { { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "14.900 ns" { sci:inst2|scir[1] sci:inst2|process0~21 sci:inst2|process0~22 sci:inst2|Data_out[0]~15 sci:inst2|Data_out[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.900 ns" { sci:inst2|scir[1] sci:inst2|process0~21 sci:inst2|process0~22 sci:inst2|Data_out[0]~15 sci:inst2|Data_out[6] } { 0.000ns 2.200ns 0.600ns 2.600ns 2.400ns } { 0.000ns 1.800ns 2.300ns 1.800ns 1.200ns } } } { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|Data_out[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|Data_out[6] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/chairang/k5/db/total_cmp.qrpt" "" { Report "E:/chairang/k5/db/total_cmp.qrpt" Compiler "total" "UNKNOWN" "V1" "E:/chairang/k5/db/total.quartus_db" { Floorplan "E:/chairang/k5/" "" "12.300 ns" { clk_1MHz count26:inst|clkout sci:inst2|scir[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.300 ns" { clk_1MHz clk_1MHz~out count26:inst|clkout sci:inst2|scir[1] } { 0.000ns 0.000ns 2.500ns 5.900ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}