📄 display_6_led.tan.qmsg

📁 串口通信实验程序
💻 QMSG
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{ "Info" "ITDB_TSU_RESULT" "sci:inst2\|scir\[3\] RXD clk_1MHz 2.916 ns register " "Info: tsu for register \"sci:inst2\|scir\[3\]\" (data pin = \"RXD\", clock pin = \"clk_1MHz\") is 2.916 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.749 ns + Longest pin register " "Info: + Longest pin to register delay is 5.749 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.972 ns) 0.972 ns RXD 1 PIN PIN_E13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.972 ns) = 0.972 ns; Loc. = PIN_E13; Fanout = 3; PIN Node = 'RXD'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { RXD } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 112 -16 152 128 "RXD" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.833 ns) + CELL(0.075 ns) 4.880 ns RXD~7 2 COMB LC_X24_Y30_N6 3 " "Info: 2: + IC(3.833 ns) + CELL(0.075 ns) = 4.880 ns; Loc. = LC_X24_Y30_N6; Fanout = 3; COMB Node = 'RXD~7'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "3.908 ns" { RXD RXD~7 } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 112 -16 152 128 "RXD" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.085 ns) 5.749 ns sci:inst2\|scir\[3\] 3 REG LC_X21_Y30_N4 7 " "Info: 3: + IC(0.784 ns) + CELL(0.085 ns) = 5.749 ns; Loc. = LC_X21_Y30_N4; Fanout = 7; REG Node = 'sci:inst2\|scir\[3\]'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.869 ns" { RXD~7 sci:inst2|scir[3] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.132 ns 19.69 % " "Info: Total cell delay = 1.132 ns ( 19.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.617 ns 80.31 % " "Info: Total interconnect delay = 4.617 ns ( 80.31 % )" {  } {  } 0}  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "5.749 ns" { RXD RXD~7 sci:inst2|scir[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.749 ns" { RXD RXD~out0 RXD~7 sci:inst2|scir[3] } { 0.000ns 0.000ns 3.833ns 0.784ns } { 0.000ns 0.972ns 0.075ns 0.085ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz destination 2.843 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_1MHz\" to destination register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk_1MHz 1 CLK PIN_L2 38 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 38; CLK Node = 'clk_1MHz'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 40 -8 160 56 "clk_1MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.576 ns) + CELL(0.542 ns) 2.843 ns sci:inst2\|scir\[3\] 2 REG LC_X21_Y30_N4 7 " "Info: 2: + IC(1.576 ns) + CELL(0.542 ns) = 2.843 ns; Loc. = LC_X21_Y30_N4; Fanout = 7; REG Node = 'sci:inst2\|scir\[3\]'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.118 ns" { clk_1MHz sci:inst2|scir[3] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.57 % " "Info: Total cell delay = 1.267 ns ( 44.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.576 ns 55.43 % " "Info: Total interconnect delay = 1.576 ns ( 55.43 % )" {  } {  } 0}  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.843 ns" { clk_1MHz sci:inst2|scir[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.843 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|scir[3] } { 0.000ns 0.000ns 1.576ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "5.749 ns" { RXD RXD~7 sci:inst2|scir[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.749 ns" { RXD RXD~out0 RXD~7 sci:inst2|scir[3] } { 0.000ns 0.000ns 3.833ns 0.784ns } { 0.000ns 0.972ns 0.075ns 0.085ns } } } { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.843 ns" { clk_1MHz sci:inst2|scir[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.843 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|scir[3] } { 0.000ns 0.000ns 1.576ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_1MHz TXD sci:inst2\|scir\[2\] 10.107 ns register " "Info: tco from clock \"clk_1MHz\" to destination pin \"TXD\" through register \"sci:inst2\|scir\[2\]\" is 10.107 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz source 2.843 ns + Longest register " "Info: + Longest clock path from clock \"clk_1MHz\" to source register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk_1MHz 1 CLK PIN_L2 38 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 38; CLK Node = 'clk_1MHz'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 40 -8 160 56 "clk_1MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.576 ns) + CELL(0.542 ns) 2.843 ns sci:inst2\|scir\[2\] 2 REG LC_X21_Y30_N3 8 " "Info: 2: + IC(1.576 ns) + CELL(0.542 ns) = 2.843 ns; Loc. = LC_X21_Y30_N3; Fanout = 8; REG Node = 'sci:inst2\|scir\[2\]'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.118 ns" { clk_1MHz sci:inst2|scir[2] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.57 % " "Info: Total cell delay = 1.267 ns ( 44.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.576 ns 55.43 % " "Info: Total interconnect delay = 1.576 ns ( 55.43 % )" {  } {  } 0}  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.843 ns" { clk_1MHz sci:inst2|scir[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.843 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|scir[2] } { 0.000ns 0.000ns 1.576ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.108 ns + Longest register pin " "Info: + Longest register to pin delay is 7.108 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sci:inst2\|scir\[2\] 1 REG LC_X21_Y30_N3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y30_N3; Fanout = 8; REG Node = 'sci:inst2\|scir\[2\]'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { sci:inst2|scir[2] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.280 ns) 1.523 ns sci:inst2\|Txd~171 2 COMB LC_X22_Y28_N5 1 " "Info: 2: + IC(1.243 ns) + CELL(0.280 ns) = 1.523 ns; Loc. = LC_X22_Y28_N5; Fanout = 1; COMB Node = 'sci:inst2\|Txd~171'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "1.523 ns" { sci:inst2|scir[2] sci:inst2|Txd~171 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.280 ns) 2.105 ns sci:inst2\|Txd~172 3 COMB LC_X22_Y28_N8 1 " "Info: 3: + IC(0.302 ns) + CELL(0.280 ns) = 2.105 ns; Loc. = LC_X22_Y28_N8; Fanout = 1; COMB Node = 'sci:inst2\|Txd~172'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.582 ns" { sci:inst2|Txd~171 sci:inst2|Txd~172 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.896 ns) + CELL(0.183 ns) 3.184 ns sci:inst2\|Txd~173 4 COMB LC_X22_Y30_N4 1 " "Info: 4: + IC(0.896 ns) + CELL(0.183 ns) = 3.184 ns; Loc. = LC_X22_Y30_N4; Fanout = 1; COMB Node = 'sci:inst2\|Txd~173'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "1.079 ns" { sci:inst2|Txd~172 sci:inst2|Txd~173 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.075 ns) 3.585 ns sci:inst2\|Txd~176 5 COMB LC_X22_Y30_N7 1 " "Info: 5: + IC(0.326 ns) + CELL(0.075 ns) = 3.585 ns; Loc. = LC_X22_Y30_N7; Fanout = 1; COMB Node = 'sci:inst2\|Txd~176'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.401 ns" { sci:inst2|Txd~173 sci:inst2|Txd~176 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.119 ns) + CELL(2.404 ns) 7.108 ns TXD 6 PIN PIN_C14 0 " "Info: 6: + IC(1.119 ns) + CELL(2.404 ns) = 7.108 ns; Loc. = PIN_C14; Fanout = 0; PIN Node = 'TXD'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "3.523 ns" { sci:inst2|Txd~176 TXD } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 72 640 816 88 "TXD" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.222 ns 45.33 % " "Info: Total cell delay = 3.222 ns ( 45.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.886 ns 54.67 % " "Info: Total interconnect delay = 3.886 ns ( 54.67 % )" {  } {  } 0}  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "7.108 ns" { sci:inst2|scir[2] sci:inst2|Txd~171 sci:inst2|Txd~172 sci:inst2|Txd~173 sci:inst2|Txd~176 TXD } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.108 ns" { sci:inst2|scir[2] sci:inst2|Txd~171 sci:inst2|Txd~172 sci:inst2|Txd~173 sci:inst2|Txd~176 TXD } { 0.000ns 1.243ns 0.302ns 0.896ns 0.326ns 1.119ns } { 0.000ns 0.280ns 0.280ns 0.183ns 0.075ns 2.404ns } } }  } 0}  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.843 ns" { clk_1MHz sci:inst2|scir[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.843 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|scir[2] } { 0.000ns 0.000ns 1.576ns } { 0.000ns 0.725ns 0.542ns } } } { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "7.108 ns" { sci:inst2|scir[2] sci:inst2|Txd~171 sci:inst2|Txd~172 sci:inst2|Txd~173 sci:inst2|Txd~176 TXD } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.108 ns" { sci:inst2|scir[2] sci:inst2|Txd~171 sci:inst2|Txd~172 sci:inst2|Txd~173 sci:inst2|Txd~176 TXD } { 0.000ns 1.243ns 0.302ns 0.896ns 0.326ns 1.119ns } { 0.000ns 0.280ns 0.280ns 0.183ns 0.075ns 2.404ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sci:inst2\|Data_out\[1\] clk_1Hz clk_1MHz -1.741 ns register " "Info: th for register \"sci:inst2\|Data_out\[1\]\" (data pin = \"clk_1Hz\", clock pin = \"clk_1MHz\") is -1.741 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz destination 2.843 ns + Longest register " "Info: + Longest clock path from clock \"clk_1MHz\" to destination register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk_1MHz 1 CLK PIN_L2 38 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 38; CLK Node = 'clk_1MHz'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 40 -8 160 56 "clk_1MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.576 ns) + CELL(0.542 ns) 2.843 ns sci:inst2\|Data_out\[1\] 2 REG LC_X23_Y30_N9 1 " "Info: 2: + IC(1.576 ns) + CELL(0.542 ns) = 2.843 ns; Loc. = LC_X23_Y30_N9; Fanout = 1; REG Node = 'sci:inst2\|Data_out\[1\]'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.118 ns" { clk_1MHz sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.57 % " "Info: Total cell delay = 1.267 ns ( 44.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.576 ns 55.43 % " "Info: Total interconnect delay = 1.576 ns ( 55.43 % )" {  } {  } 0}  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.843 ns" { clk_1MHz sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.843 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|Data_out[1] } { 0.000ns 0.000ns 1.576ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.684 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk_1Hz 1 CLK PIN_L3 18 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 18; CLK Node = 'clk_1Hz'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { clk_1Hz } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 216 0 168 232 "clk_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.009 ns) + CELL(0.366 ns) 3.203 ns sci:inst2\|Data_out\[4\]~11 2 COMB LC_X22_Y30_N5 8 " "Info: 2: + IC(2.009 ns) + CELL(0.366 ns) = 3.203 ns; Loc. = LC_X22_Y30_N5; Fanout = 8; COMB Node = 'sci:inst2\|Data_out\[4\]~11'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.375 ns" { clk_1Hz sci:inst2|Data_out[4]~11 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.705 ns) 4.684 ns sci:inst2\|Data_out\[1\] 3 REG LC_X23_Y30_N9 1 " "Info: 3: + IC(0.776 ns) + CELL(0.705 ns) = 4.684 ns; Loc. = LC_X23_Y30_N9; Fanout = 1; REG Node = 'sci:inst2\|Data_out\[1\]'" {  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "1.481 ns" { sci:inst2|Data_out[4]~11 sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.899 ns 40.54 % " "Info: Total cell delay = 1.899 ns ( 40.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.785 ns 59.46 % " "Info: Total interconnect delay = 2.785 ns ( 59.46 % )" {  } {  } 0}  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "4.684 ns" { clk_1Hz sci:inst2|Data_out[4]~11 sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.684 ns" { clk_1Hz clk_1Hz~out0 sci:inst2|Data_out[4]~11 sci:inst2|Data_out[1] } { 0.000ns 0.000ns 2.009ns 0.776ns } { 0.000ns 0.828ns 0.366ns 0.705ns } } }  } 0}  } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.843 ns" { clk_1MHz sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.843 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|Data_out[1] } { 0.000ns 0.000ns 1.576ns } { 0.000ns 0.725ns 0.542ns } } } { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "4.684 ns" { clk_1Hz sci:inst2|Data_out[4]~11 sci:inst2|Data_out[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.684 ns" { clk_1Hz clk_1Hz~out0 sci:inst2|Data_out[4]~11 sci:inst2|Data_out[1] } { 0.000ns 0.000ns 2.009ns 0.776ns } { 0.000ns 0.828ns 0.366ns 0.705ns } } }  } 0}
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