📄 display_6_led.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_1MHz " "Info: Assuming node \"clk_1MHz\" is an undefined clock" { } { { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 40 -8 160 56 "clk_1MHz" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_1MHz" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_1Hz " "Info: Assuming node \"clk_1Hz\" is an undefined clock" { } { { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 216 0 168 232 "clk_1Hz" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_1Hz" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_1MHz register sci:inst2\|scir\[3\] register sci:inst2\|Data_out\[5\] 305.16 MHz 3.277 ns Internal " "Info: Clock \"clk_1MHz\" has Internal fmax of 305.16 MHz between source register \"sci:inst2\|scir\[3\]\" and destination register \"sci:inst2\|Data_out\[5\]\" (period= 3.277 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.109 ns + Longest register register " "Info: + Longest register to register delay is 3.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sci:inst2\|scir\[3\] 1 REG LC_X21_Y30_N4 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y30_N4; Fanout = 7; REG Node = 'sci:inst2\|scir\[3\]'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { sci:inst2|scir[3] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.561 ns) + CELL(0.280 ns) 0.841 ns sci:inst2\|scir~243 2 COMB LC_X22_Y30_N1 1 " "Info: 2: + IC(0.561 ns) + CELL(0.280 ns) = 0.841 ns; Loc. = LC_X22_Y30_N1; Fanout = 1; COMB Node = 'sci:inst2\|scir~243'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.841 ns" { sci:inst2|scir[3] sci:inst2|scir~243 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 1.050 ns sci:inst2\|process0~21 3 COMB LC_X22_Y30_N2 4 " "Info: 3: + IC(0.134 ns) + CELL(0.075 ns) = 1.050 ns; Loc. = LC_X22_Y30_N2; Fanout = 4; COMB Node = 'sci:inst2\|process0~21'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.209 ns" { sci:inst2|scir~243 sci:inst2|process0~21 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.075 ns) 1.468 ns sci:inst2\|Data_out\[4\]~11 4 COMB LC_X22_Y30_N5 8 " "Info: 4: + IC(0.343 ns) + CELL(0.075 ns) = 1.468 ns; Loc. = LC_X22_Y30_N5; Fanout = 8; COMB Node = 'sci:inst2\|Data_out\[4\]~11'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.418 ns" { sci:inst2|process0~21 sci:inst2|Data_out[4]~11 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.936 ns) + CELL(0.705 ns) 3.109 ns sci:inst2\|Data_out\[5\] 5 REG LC_X23_Y29_N0 1 " "Info: 5: + IC(0.936 ns) + CELL(0.705 ns) = 3.109 ns; Loc. = LC_X23_Y29_N0; Fanout = 1; REG Node = 'sci:inst2\|Data_out\[5\]'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "1.641 ns" { sci:inst2|Data_out[4]~11 sci:inst2|Data_out[5] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.135 ns 36.51 % " "Info: Total cell delay = 1.135 ns ( 36.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.974 ns 63.49 % " "Info: Total interconnect delay = 1.974 ns ( 63.49 % )" { } { } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "3.109 ns" { sci:inst2|scir[3] sci:inst2|scir~243 sci:inst2|process0~21 sci:inst2|Data_out[4]~11 sci:inst2|Data_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { sci:inst2|scir[3] sci:inst2|scir~243 sci:inst2|process0~21 sci:inst2|Data_out[4]~11 sci:inst2|Data_out[5] } { 0.000ns 0.561ns 0.134ns 0.343ns 0.936ns } { 0.000ns 0.280ns 0.075ns 0.075ns 0.705ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns - Smallest " "Info: - Smallest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz destination 2.841 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_1MHz\" to destination register is 2.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk_1MHz 1 CLK PIN_L2 38 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 38; CLK Node = 'clk_1MHz'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 40 -8 160 56 "clk_1MHz" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.574 ns) + CELL(0.542 ns) 2.841 ns sci:inst2\|Data_out\[5\] 2 REG LC_X23_Y29_N0 1 " "Info: 2: + IC(1.574 ns) + CELL(0.542 ns) = 2.841 ns; Loc. = LC_X23_Y29_N0; Fanout = 1; REG Node = 'sci:inst2\|Data_out\[5\]'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.116 ns" { clk_1MHz sci:inst2|Data_out[5] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.60 % " "Info: Total cell delay = 1.267 ns ( 44.60 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.574 ns 55.40 % " "Info: Total interconnect delay = 1.574 ns ( 55.40 % )" { } { } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.841 ns" { clk_1MHz sci:inst2|Data_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.841 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|Data_out[5] } { 0.000ns 0.000ns 1.574ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1MHz source 2.843 ns - Longest register " "Info: - Longest clock path from clock \"clk_1MHz\" to source register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk_1MHz 1 CLK PIN_L2 38 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 38; CLK Node = 'clk_1MHz'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { clk_1MHz } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 40 -8 160 56 "clk_1MHz" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.576 ns) + CELL(0.542 ns) 2.843 ns sci:inst2\|scir\[3\] 2 REG LC_X21_Y30_N4 7 " "Info: 2: + IC(1.576 ns) + CELL(0.542 ns) = 2.843 ns; Loc. = LC_X21_Y30_N4; Fanout = 7; REG Node = 'sci:inst2\|scir\[3\]'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.118 ns" { clk_1MHz sci:inst2|scir[3] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.57 % " "Info: Total cell delay = 1.267 ns ( 44.57 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.576 ns 55.43 % " "Info: Total interconnect delay = 1.576 ns ( 55.43 % )" { } { } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.843 ns" { clk_1MHz sci:inst2|scir[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.843 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|scir[3] } { 0.000ns 0.000ns 1.576ns } { 0.000ns 0.725ns 0.542ns } } } } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.841 ns" { clk_1MHz sci:inst2|Data_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.841 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|Data_out[5] } { 0.000ns 0.000ns 1.574ns } { 0.000ns 0.725ns 0.542ns } } } { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.843 ns" { clk_1MHz sci:inst2|scir[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.843 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|scir[3] } { 0.000ns 0.000ns 1.576ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 9 -1 0 } } } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "3.109 ns" { sci:inst2|scir[3] sci:inst2|scir~243 sci:inst2|process0~21 sci:inst2|Data_out[4]~11 sci:inst2|Data_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.109 ns" { sci:inst2|scir[3] sci:inst2|scir~243 sci:inst2|process0~21 sci:inst2|Data_out[4]~11 sci:inst2|Data_out[5] } { 0.000ns 0.561ns 0.134ns 0.343ns 0.936ns } { 0.000ns 0.280ns 0.075ns 0.075ns 0.705ns } } } { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.841 ns" { clk_1MHz sci:inst2|Data_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.841 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|Data_out[5] } { 0.000ns 0.000ns 1.574ns } { 0.000ns 0.725ns 0.542ns } } } { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.843 ns" { clk_1MHz sci:inst2|scir[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.843 ns" { clk_1MHz clk_1MHz~out0 sci:inst2|scir[3] } { 0.000ns 0.000ns 1.576ns } { 0.000ns 0.725ns 0.542ns } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_1Hz register register count8:inst\|q_out\[2\] count8:inst\|q_out\[5\] 422.12 MHz Internal " "Info: Clock \"clk_1Hz\" Internal fmax is restricted to 422.12 MHz between source register \"count8:inst\|q_out\[2\]\" and destination register \"count8:inst\|q_out\[5\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.607 ns + Longest register register " "Info: + Longest register to register delay is 1.607 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count8:inst\|q_out\[2\] 1 REG LC_X23_Y28_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y28_N2; Fanout = 4; REG Node = 'count8:inst\|q_out\[2\]'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { count8:inst|q_out[2] } "NODE_NAME" } "" } } { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.443 ns) 0.841 ns count8:inst\|q_out\[2\]~97 2 COMB LC_X23_Y28_N2 2 " "Info: 2: + IC(0.398 ns) + CELL(0.443 ns) = 0.841 ns; Loc. = LC_X23_Y28_N2; Fanout = 2; COMB Node = 'count8:inst\|q_out\[2\]~97'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.841 ns" { count8:inst|q_out[2] count8:inst|q_out[2]~97 } "NODE_NAME" } "" } } { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 0.899 ns count8:inst\|q_out\[3\]~105 3 COMB LC_X23_Y28_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.899 ns; Loc. = LC_X23_Y28_N3; Fanout = 2; COMB Node = 'count8:inst\|q_out\[3\]~105'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.058 ns" { count8:inst|q_out[2]~97 count8:inst|q_out[3]~105 } "NODE_NAME" } "" } } { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 1.029 ns count8:inst\|q_out\[4\]~89 4 COMB LC_X23_Y28_N4 3 " "Info: 4: + IC(0.000 ns) + CELL(0.130 ns) = 1.029 ns; Loc. = LC_X23_Y28_N4; Fanout = 3; COMB Node = 'count8:inst\|q_out\[4\]~89'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.130 ns" { count8:inst|q_out[3]~105 count8:inst|q_out[4]~89 } "NODE_NAME" } "" } } { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.578 ns) 1.607 ns count8:inst\|q_out\[5\] 5 REG LC_X23_Y28_N5 4 " "Info: 5: + IC(0.000 ns) + CELL(0.578 ns) = 1.607 ns; Loc. = LC_X23_Y28_N5; Fanout = 4; REG Node = 'count8:inst\|q_out\[5\]'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "0.578 ns" { count8:inst|q_out[4]~89 count8:inst|q_out[5] } "NODE_NAME" } "" } } { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.209 ns 75.23 % " "Info: Total cell delay = 1.209 ns ( 75.23 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.398 ns 24.77 % " "Info: Total interconnect delay = 0.398 ns ( 24.77 % )" { } { } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "1.607 ns" { count8:inst|q_out[2] count8:inst|q_out[2]~97 count8:inst|q_out[3]~105 count8:inst|q_out[4]~89 count8:inst|q_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.607 ns" { count8:inst|q_out[2] count8:inst|q_out[2]~97 count8:inst|q_out[3]~105 count8:inst|q_out[4]~89 count8:inst|q_out[5] } { 0.000ns 0.398ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.443ns 0.058ns 0.130ns 0.578ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1Hz destination 2.950 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_1Hz\" to destination register is 2.950 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk_1Hz 1 CLK PIN_L3 18 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 18; CLK Node = 'clk_1Hz'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { clk_1Hz } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 216 0 168 232 "clk_1Hz" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.580 ns) + CELL(0.542 ns) 2.950 ns count8:inst\|q_out\[5\] 2 REG LC_X23_Y28_N5 4 " "Info: 2: + IC(1.580 ns) + CELL(0.542 ns) = 2.950 ns; Loc. = LC_X23_Y28_N5; Fanout = 4; REG Node = 'count8:inst\|q_out\[5\]'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.122 ns" { clk_1Hz count8:inst|q_out[5] } "NODE_NAME" } "" } } { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns 46.44 % " "Info: Total cell delay = 1.370 ns ( 46.44 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.580 ns 53.56 % " "Info: Total interconnect delay = 1.580 ns ( 53.56 % )" { } { } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.950 ns" { clk_1Hz count8:inst|q_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.950 ns" { clk_1Hz clk_1Hz~out0 count8:inst|q_out[5] } { 0.000ns 0.000ns 1.580ns } { 0.000ns 0.828ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1Hz source 2.950 ns - Longest register " "Info: - Longest clock path from clock \"clk_1Hz\" to source register is 2.950 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk_1Hz 1 CLK PIN_L3 18 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 18; CLK Node = 'clk_1Hz'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { clk_1Hz } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 216 0 168 232 "clk_1Hz" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.580 ns) + CELL(0.542 ns) 2.950 ns count8:inst\|q_out\[2\] 2 REG LC_X23_Y28_N2 4 " "Info: 2: + IC(1.580 ns) + CELL(0.542 ns) = 2.950 ns; Loc. = LC_X23_Y28_N2; Fanout = 4; REG Node = 'count8:inst\|q_out\[2\]'" { } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.122 ns" { clk_1Hz count8:inst|q_out[2] } "NODE_NAME" } "" } } { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns 46.44 % " "Info: Total cell delay = 1.370 ns ( 46.44 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.580 ns 53.56 % " "Info: Total interconnect delay = 1.580 ns ( 53.56 % )" { } { } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.950 ns" { clk_1Hz count8:inst|q_out[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.950 ns" { clk_1Hz clk_1Hz~out0 count8:inst|q_out[2] } { 0.000ns 0.000ns 1.580ns } { 0.000ns 0.828ns 0.542ns } } } } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.950 ns" { clk_1Hz count8:inst|q_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.950 ns" { clk_1Hz clk_1Hz~out0 count8:inst|q_out[5] } { 0.000ns 0.000ns 1.580ns } { 0.000ns 0.828ns 0.542ns } } } { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.950 ns" { clk_1Hz count8:inst|q_out[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.950 ns" { clk_1Hz clk_1Hz~out0 count8:inst|q_out[2] } { 0.000ns 0.000ns 1.580ns } { 0.000ns 0.828ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "1.607 ns" { count8:inst|q_out[2] count8:inst|q_out[2]~97 count8:inst|q_out[3]~105 count8:inst|q_out[4]~89 count8:inst|q_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.607 ns" { count8:inst|q_out[2] count8:inst|q_out[2]~97 count8:inst|q_out[3]~105 count8:inst|q_out[4]~89 count8:inst|q_out[5] } { 0.000ns 0.398ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.443ns 0.058ns 0.130ns 0.578ns } } } { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.950 ns" { clk_1Hz count8:inst|q_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.950 ns" { clk_1Hz clk_1Hz~out0 count8:inst|q_out[5] } { 0.000ns 0.000ns 1.580ns } { 0.000ns 0.828ns 0.542ns } } } { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "2.950 ns" { clk_1Hz count8:inst|q_out[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.950 ns" { clk_1Hz clk_1Hz~out0 count8:inst|q_out[2] } { 0.000ns 0.000ns 1.580ns } { 0.000ns 0.828ns 0.542ns } } } } 0} } { { "G:/20036016_5/db/display_6_led_cmp.qrpt" "" { Report "G:/20036016_5/db/display_6_led_cmp.qrpt" Compiler "display_6_led" "UNKNOWN" "V1" "G:/20036016_5/db/display_6_led.quartus_db" { Floorplan "G:/20036016_5/" "" "" { count8:inst|q_out[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { count8:inst|q_out[5] } { } { } } } { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 10 -1 0 } } } 0}
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