sci.fit.qmsg

串口通信实验程序

{ "Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "22 unused 3.30 11 11 0 " "Info: Number of I/O pins in group: 22 (unused VREF, 3.30 VCCIO, 11 input, 11 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 29 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 30 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 51 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 51 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 2 27 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  27 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 1 28 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 52 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 51 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.067 ns register register " "Info: Estimated most critical path is register to register delay of 3.067 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scir\[4\] 1 REG LAB_X41_Y23 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X41_Y23; Fanout = 6; REG Node = 'scir\[4\]'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { scir[4] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 83 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.311 ns) + CELL(0.366 ns) 0.677 ns scir~167 2 COMB LAB_X40_Y23 3 " "Info: 2: + IC(0.311 ns) + CELL(0.366 ns) = 0.677 ns; Loc. = LAB_X40_Y23; Fanout = 3; COMB Node = 'scir~167'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "0.677 ns" { scir[4] scir~167 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 83 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.188 ns) + CELL(0.280 ns) 1.145 ns process0~21 3 COMB LAB_X40_Y23 3 " "Info: 3: + IC(0.188 ns) + CELL(0.280 ns) = 1.145 ns; Loc. = LAB_X40_Y23; Fanout = 3; COMB Node = 'process0~21'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "0.468 ns" { scir~167 process0~21 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.102 ns) + CELL(0.366 ns) 1.613 ns Data_out\[7\]~8 4 COMB LAB_X40_Y23 8 " "Info: 4: + IC(0.102 ns) + CELL(0.366 ns) = 1.613 ns; Loc. = LAB_X40_Y23; Fanout = 8; COMB Node = 'Data_out\[7\]~8'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "0.468 ns" { process0~21 Data_out[7]~8 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.749 ns) + CELL(0.705 ns) 3.067 ns Data_out\[1\]~reg0 5 REG LAB_X44_Y23 1 " "Info: 5: + IC(0.749 ns) + CELL(0.705 ns) = 3.067 ns; Loc. = LAB_X44_Y23; Fanout = 1; REG Node = 'Data_out\[1\]~reg0'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "1.454 ns" { Data_out[7]~8 Data_out[1]~reg0 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.717 ns 55.98 % " "Info: Total cell delay = 1.717 ns ( 55.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.350 ns 44.02 % " "Info: Total interconnect delay = 1.350 ns ( 44.02 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "3.067 ns" { scir[4] scir~167 process0~21 Data_out[7]~8 Data_out[1]~reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 12 19:55:15 2006 " "Info: Processing ended: Thu Jan 12 19:55:15 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Info: Elapsed time: 00:00:23" {  } {  } 0}  } {  } 0}