total.map.qmsg

串口通信实验程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 13 16:45:44 2006 " "Info: Processing started: Fri Jan 13 16:45:44 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off total -c total " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off total -c total" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count26.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count26.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count26-rtl " "Info: Found design unit 1: count26-rtl" {  } { { "count26.vhd" "" { Text "E:/chairang/k5/count26.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 count26 " "Info: Found entity 1: count26" {  } { { "count26.vhd" "" { Text "E:/chairang/k5/count26.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count8-rtl " "Info: Found design unit 1: count8-rtl" {  } { { "count8.vhd" "" { Text "E:/chairang/k5/count8.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 count8 " "Info: Found entity 1: count8" {  } { { "count8.vhd" "" { Text "E:/chairang/k5/count8.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display_6_led.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display_6_led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display_6_led-behave " "Info: Found design unit 1: display_6_led-behave" {  } { { "display_6_led.vhd" "" { Text "E:/chairang/k5/display_6_led.vhd" 25 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 display_6_led " "Info: Found entity 1: display_6_led" {  } { { "display_6_led.vhd" "" { Text "E:/chairang/k5/display_6_led.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sci.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sci.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sci-rtl " "Info: Found design unit 1: sci-rtl" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sci " "Info: Found entity 1: sci" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "total.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file total.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 total " "Info: Found entity 1: total" {  } { { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "total " "Info: Elaborating entity \"total\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_INCONSISTENT_DIMENSION" "" "Warning: Found inconsistent dimensions" {  } { { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 440 120 296 456 "d\[3..0\]" "" } { 232 264 305 248 "d\[7..0\]" "" } { 392 608 784 408 "D" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display_6_led display_6_led:inst3 " "Info: Elaborating entity \"display_6_led\" for hierarchy \"display_6_led:inst3\"" {  } { { "total.bdf" "inst3" { Schematic "E:/chairang/k5/total.bdf" { { 272 480 608 496 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count26 count26:inst " "Info: Elaborating entity \"count26\" for hierarchy \"count26:inst\"" {  } { { "total.bdf" "inst" { Schematic "E:/chairang/k5/total.bdf" { { 64 168 264 160 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sci sci:inst2 " "Info: Elaborating entity \"sci\" for hierarchy \"sci:inst2\"" {  } { { "total.bdf" "inst2" { Schematic "E:/chairang/k5/total.bdf" { { 40 464 648 200 "inst2" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cs sci.vhd(69) " "Warning: VHDL Process Statement warning at sci.vhd(69): signal \"cs\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 69 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(134) " "Warning: VHDL Process Statement warning at sci.vhd(134): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(135) " "Warning: VHDL Process Statement warning at sci.vhd(135): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 135 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(136) " "Warning: VHDL Process Statement warning at sci.vhd(136): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 136 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(137) " "Warning: VHDL Process Statement warning at sci.vhd(137): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(138) " "Warning: VHDL Process Statement warning at sci.vhd(138): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(139) " "Warning: VHDL Process Statement warning at sci.vhd(139): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(140) " "Warning: VHDL Process Statement warning at sci.vhd(140): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(141) " "Warning: VHDL Process Statement warning at sci.vhd(141): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 141 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count8 count8:inst1 " "Info: Elaborating entity \"count8\" for hierarchy \"count8:inst1\"" {  } { { "total.bdf" "inst1" { Schematic "E:/chairang/k5/total.bdf" { { 216 168 264 312 "inst1" "" } } } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "count8:inst1\|q_out\[0\]~8 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: \"count8:inst1\|q_out\[0\]~8\"" {  } { { "count8.vhd" "q_out\[0\]~8" { Text "E:/chairang/k5/count8.vhd" 10 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "display_6_led:inst3\|q\[0\]~6 6 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: \"display_6_led:inst3\|q\[0\]~6\"" {  } { { "display_6_led.vhd" "q\[0\]~6" { Text "E:/chairang/k5/display_6_led.vhd" 26 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "count26:inst\|bcd1\[0\]~12 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"count26:inst\|bcd1\[0\]~12\"" {  } { { "count26.vhd" "bcd1\[0\]~12" { Text "E:/chairang/k5/count26.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sci:inst2\|txdf sci:inst2\|tdempty " "Info: Duplicate register \"sci:inst2\|txdf\" merged to single register \"sci:inst2\|tdempty\"" {  } { { "sci.vhd" "" { Text "E:/chairang/k5/sci.vhd" 22 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "DP GND " "Warning: Pin \"DP\" stuck at GND" {  } { { "total.bdf" "" { Schematic "E:/chairang/k5/total.bdf" { { 456 608 784 472 "DP" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "122 " "Info: Implemented 122 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "101 " "Info: Implemented 101 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 13 16:45:48 2006 " "Info: Processing ended: Fri Jan 13 16:45:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}