display_6_led.map.qmsg

串口通信实验程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 13 11:13:20 2006 " "Info: Processing started: Fri Jan 13 11:13:20 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off display_6_led -c display_6_led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off display_6_led -c display_6_led" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count26.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count26.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count26-rtl " "Info: Found design unit 1: count26-rtl" {  } { { "count26.vhd" "" { Text "G:/20036016_5/count26.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 count26 " "Info: Found entity 1: count26" {  } { { "count26.vhd" "" { Text "G:/20036016_5/count26.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count8-rtl " "Info: Found design unit 1: count8-rtl" {  } { { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 count8 " "Info: Found entity 1: count8" {  } { { "count8.vhd" "" { Text "G:/20036016_5/count8.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display_6_led.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display_6_led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display_6_led-behave " "Info: Found design unit 1: display_6_led-behave" {  } { { "display_6_led.vhd" "" { Text "G:/20036016_5/display_6_led.vhd" 25 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 display_6_led " "Info: Found entity 1: display_6_led" {  } { { "display_6_led.vhd" "" { Text "G:/20036016_5/display_6_led.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sci.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sci.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sci-rtl " "Info: Found design unit 1: sci-rtl" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sci " "Info: Found entity 1: sci" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "total.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file total.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 total " "Info: Found entity 1: total" {  } { { "total.bdf" "" { Schematic "G:/20036016_5/total.bdf" { } } }  } 0}  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/20036016_5/display_6_led.vhd " "Warning: Can't analyze file -- file E:/20036016_5/display_6_led.vhd is missing" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display_6_led display_6_led:inst3 " "Info: Elaborating entity \"display_6_led\" for hierarchy \"display_6_led:inst3\"" {  } { { "Block1.bdf" "inst3" { Schematic "G:/20036016_5/Block1.bdf" { { 248 344 472 472 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sci sci:inst2 " "Info: Elaborating entity \"sci\" for hierarchy \"sci:inst2\"" {  } { { "Block1.bdf" "inst2" { Schematic "G:/20036016_5/Block1.bdf" { { 48 456 640 208 "inst2" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cs sci.vhd(69) " "Warning: VHDL Process Statement warning at sci.vhd(69): signal \"cs\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 69 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(134) " "Warning: VHDL Process Statement warning at sci.vhd(134): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(135) " "Warning: VHDL Process Statement warning at sci.vhd(135): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 135 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(136) " "Warning: VHDL Process Statement warning at sci.vhd(136): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 136 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(137) " "Warning: VHDL Process Statement warning at sci.vhd(137): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(138) " "Warning: VHDL Process Statement warning at sci.vhd(138): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(139) " "Warning: VHDL Process Statement warning at sci.vhd(139): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(140) " "Warning: VHDL Process Statement warning at sci.vhd(140): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(141) " "Warning: VHDL Process Statement warning at sci.vhd(141): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 141 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count8 count8:inst " "Info: Elaborating entity \"count8\" for hierarchy \"count8:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "G:/20036016_5/Block1.bdf" { { 88 200 296 184 "inst" "" } } } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sci:inst2\|tdempty sci:inst2\|txdf " "Info: Duplicate register \"sci:inst2\|tdempty\" merged to single register \"sci:inst2\|txdf\"" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "sci:inst2\|din_latch\[0\] count8:inst\|q_out\[0\] " "Info: Duplicate register \"sci:inst2\|din_latch\[0\]\" merged to single register \"count8:inst\|q_out\[0\]\", power-up level changed" {  } { { "sci.vhd" "" { Text "G:/20036016_5/sci.vhd" 20 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "DP GND " "Warning: Pin \"DP\" stuck at GND" {  } { { "Block1.bdf" "" { Schematic "G:/20036016_5/Block1.bdf" { { 432 472 648 448 "DP" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "92 " "Info: Implemented 92 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "75 " "Info: Implemented 75 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 13 11:13:29 2006 " "Info: Processing ended: Fri Jan 13 11:13:29 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}