sci.tan.qmsg

串口通信实验程序

{ "Info" "ITDB_TSU_RESULT" "Data_out\[1\]~reg0 rd clk 4.036 ns register " "Info: tsu for register \"Data_out\[1\]~reg0\" (data pin = \"rd\", clock pin = \"clk\") is 4.036 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.787 ns + Longest pin register " "Info: + Longest pin to register delay is 6.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns rd 1 PIN PIN_G8 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_G8; Fanout = 2; PIN Node = 'rd'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { rd } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.872 ns) + CELL(0.366 ns) 5.325 ns Data_out\[7\]~8 2 COMB LC_X40_Y23_N7 8 " "Info: 2: + IC(3.872 ns) + CELL(0.366 ns) = 5.325 ns; Loc. = LC_X40_Y23_N7; Fanout = 8; COMB Node = 'Data_out\[7\]~8'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "4.238 ns" { rd Data_out[7]~8 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.705 ns) 6.787 ns Data_out\[1\]~reg0 3 REG LC_X44_Y23_N4 1 " "Info: 3: + IC(0.757 ns) + CELL(0.705 ns) = 6.787 ns; Loc. = LC_X44_Y23_N4; Fanout = 1; REG Node = 'Data_out\[1\]~reg0'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "1.462 ns" { Data_out[7]~8 Data_out[1]~reg0 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns 31.80 % " "Info: Total cell delay = 2.158 ns ( 31.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.629 ns 68.20 % " "Info: Total interconnect delay = 4.629 ns ( 68.20 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "6.787 ns" { rd Data_out[7]~8 Data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.787 ns" { rd rd~out0 Data_out[7]~8 Data_out[1]~reg0 } { 0.000ns 0.000ns 3.872ns 0.757ns } { 0.000ns 1.087ns 0.366ns 0.705ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.761 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { clk } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.542 ns) 2.761 ns Data_out\[1\]~reg0 2 REG LC_X44_Y23_N4 1 " "Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X44_Y23_N4; Fanout = 1; REG Node = 'Data_out\[1\]~reg0'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.036 ns" { clk Data_out[1]~reg0 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.89 % " "Info: Total cell delay = 1.267 ns ( 45.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns 54.11 % " "Info: Total interconnect delay = 1.494 ns ( 54.11 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk Data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 Data_out[1]~reg0 } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "6.787 ns" { rd Data_out[7]~8 Data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.787 ns" { rd rd~out0 Data_out[7]~8 Data_out[1]~reg0 } { 0.000ns 0.000ns 3.872ns 0.757ns } { 0.000ns 1.087ns 0.366ns 0.705ns } } } { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk Data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 Data_out[1]~reg0 } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Txd scir\[2\] 10.324 ns register " "Info: tco from clock \"clk\" to destination pin \"Txd\" through register \"scir\[2\]\" is 10.324 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.761 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { clk } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.542 ns) 2.761 ns scir\[2\] 2 REG LC_X41_Y23_N3 8 " "Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X41_Y23_N3; Fanout = 8; REG Node = 'scir\[2\]'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.036 ns" { clk scir[2] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 83 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.89 % " "Info: Total cell delay = 1.267 ns ( 45.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns 54.11 % " "Info: Total interconnect delay = 1.494 ns ( 54.11 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk scir[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 scir[2] } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 83 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.407 ns + Longest register pin " "Info: + Longest register to pin delay is 7.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scir\[2\] 1 REG LC_X41_Y23_N3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y23_N3; Fanout = 8; REG Node = 'scir\[2\]'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { scir[2] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 83 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.366 ns) 1.404 ns Mux~41 2 COMB LC_X41_Y24_N1 1 " "Info: 2: + IC(1.038 ns) + CELL(0.366 ns) = 1.404 ns; Loc. = LC_X41_Y24_N1; Fanout = 1; COMB Node = 'Mux~41'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "1.404 ns" { scir[2] Mux~41 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.310 ns) + CELL(0.280 ns) 1.994 ns Mux~42 3 COMB LC_X41_Y24_N8 1 " "Info: 3: + IC(0.310 ns) + CELL(0.280 ns) = 1.994 ns; Loc. = LC_X41_Y24_N8; Fanout = 1; COMB Node = 'Mux~42'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "0.590 ns" { Mux~41 Mux~42 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.327 ns) + CELL(0.366 ns) 2.687 ns Mux~160 4 COMB LC_X41_Y24_N3 1 " "Info: 4: + IC(0.327 ns) + CELL(0.366 ns) = 2.687 ns; Loc. = LC_X41_Y24_N3; Fanout = 1; COMB Node = 'Mux~160'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "0.693 ns" { Mux~42 Mux~160 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.495 ns) + CELL(0.366 ns) 3.548 ns Mux~161 5 COMB LC_X40_Y24_N2 1 " "Info: 5: + IC(0.495 ns) + CELL(0.366 ns) = 3.548 ns; Loc. = LC_X40_Y24_N2; Fanout = 1; COMB Node = 'Mux~161'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "0.861 ns" { Mux~160 Mux~161 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.455 ns) + CELL(2.404 ns) 7.407 ns Txd 6 PIN PIN_A6 0 " "Info: 6: + IC(1.455 ns) + CELL(2.404 ns) = 7.407 ns; Loc. = PIN_A6; Fanout = 0; PIN Node = 'Txd'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "3.859 ns" { Mux~161 Txd } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.782 ns 51.06 % " "Info: Total cell delay = 3.782 ns ( 51.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.625 ns 48.94 % " "Info: Total interconnect delay = 3.625 ns ( 48.94 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "7.407 ns" { scir[2] Mux~41 Mux~42 Mux~160 Mux~161 Txd } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "7.407 ns" { scir[2] Mux~41 Mux~42 Mux~160 Mux~161 Txd } { 0.000ns 1.038ns 0.310ns 0.327ns 0.495ns 1.455ns } { 0.000ns 0.366ns 0.280ns 0.366ns 0.366ns 2.404ns } } }  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk scir[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 scir[2] } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "7.407 ns" { scir[2] Mux~41 Mux~42 Mux~160 Mux~161 Txd } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "7.407 ns" { scir[2] Mux~41 Mux~42 Mux~160 Mux~161 Txd } { 0.000ns 1.038ns 0.310ns 0.327ns 0.495ns 1.455ns } { 0.000ns 0.366ns 0.280ns 0.366ns 0.366ns 2.404ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "txdf reset clk -0.951 ns register " "Info: th for register \"txdf\" (data pin = \"reset\", clock pin = \"clk\") is -0.951 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.761 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { clk } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.542 ns) 2.761 ns txdf 2 REG LC_X41_Y23_N0 1 " "Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X41_Y23_N0; Fanout = 1; REG Node = 'txdf'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.036 ns" { clk txdf } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 69 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.89 % " "Info: Total cell delay = 1.267 ns ( 45.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns 54.11 % " "Info: Total interconnect delay = 1.494 ns ( 54.11 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk txdf } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 txdf } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 69 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.812 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns reset 1 PIN PIN_M2 15 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 15; PIN Node = 'reset'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { reset } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.873 ns) + CELL(0.183 ns) 2.781 ns rtl~1 2 COMB LC_X41_Y23_N7 1 " "Info: 2: + IC(1.873 ns) + CELL(0.183 ns) = 2.781 ns; Loc. = LC_X41_Y23_N7; Fanout = 1; COMB Node = 'rtl~1'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.056 ns" { reset rtl~1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.705 ns) 3.812 ns txdf 3 REG LC_X41_Y23_N0 1 " "Info: 3: + IC(0.326 ns) + CELL(0.705 ns) = 3.812 ns; Loc. = LC_X41_Y23_N0; Fanout = 1; REG Node = 'txdf'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "1.031 ns" { rtl~1 txdf } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 69 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.613 ns 42.31 % " "Info: Total cell delay = 1.613 ns ( 42.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.199 ns 57.69 % " "Info: Total interconnect delay = 2.199 ns ( 57.69 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "3.812 ns" { reset rtl~1 txdf } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.812 ns" { reset reset~out0 rtl~1 txdf } { 0.000ns 0.000ns 1.873ns 0.326ns } { 0.000ns 0.725ns 0.183ns 0.705ns } } }  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk txdf } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 txdf } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "3.812 ns" { reset rtl~1 txdf } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.812 ns" { reset reset~out0 rtl~1 txdf } { 0.000ns 0.000ns 1.873ns 0.326ns } { 0.000ns 0.725ns 0.183ns 0.705ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 12 19:55:32 2006 " "Info: Processing ended: Thu Jan 12 19:55:32 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}