sci.tan.qmsg

串口通信实验程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 12 19:55:31 2006 " "Info: Processing started: Thu Jan 12 19:55:31 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off sci -c sci --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off sci -c sci --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 6 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wr " "Info: Assuming node \"wr\" is an undefined clock" {  } { { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 6 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "wr" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register scir\[2\] register Data_out\[0\]~reg0 285.8 MHz 3.499 ns Internal " "Info: Clock \"clk\" has Internal fmax of 285.8 MHz between source register \"scir\[2\]\" and destination register \"Data_out\[0\]~reg0\" (period= 3.499 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.333 ns + Longest register register " "Info: + Longest register to register delay is 3.333 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scir\[2\] 1 REG LC_X41_Y23_N3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y23_N3; Fanout = 8; REG Node = 'scir\[2\]'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { scir[2] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 83 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.366 ns) 0.946 ns scir~167 2 COMB LC_X40_Y23_N9 3 " "Info: 2: + IC(0.580 ns) + CELL(0.366 ns) = 0.946 ns; Loc. = LC_X40_Y23_N9; Fanout = 3; COMB Node = 'scir~167'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "0.946 ns" { scir[2] scir~167 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 83 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.533 ns) + CELL(0.183 ns) 1.662 ns process0~21 3 COMB LC_X40_Y23_N6 3 " "Info: 3: + IC(0.533 ns) + CELL(0.183 ns) = 1.662 ns; Loc. = LC_X40_Y23_N6; Fanout = 3; COMB Node = 'process0~21'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "0.716 ns" { scir~167 process0~21 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 1.871 ns Data_out\[7\]~8 4 COMB LC_X40_Y23_N7 8 " "Info: 4: + IC(0.134 ns) + CELL(0.075 ns) = 1.871 ns; Loc. = LC_X40_Y23_N7; Fanout = 8; COMB Node = 'Data_out\[7\]~8'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "0.209 ns" { process0~21 Data_out[7]~8 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.705 ns) 3.333 ns Data_out\[0\]~reg0 5 REG LC_X44_Y23_N2 1 " "Info: 5: + IC(0.757 ns) + CELL(0.705 ns) = 3.333 ns; Loc. = LC_X44_Y23_N2; Fanout = 1; REG Node = 'Data_out\[0\]~reg0'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "1.462 ns" { Data_out[7]~8 Data_out[0]~reg0 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.329 ns 39.87 % " "Info: Total cell delay = 1.329 ns ( 39.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.004 ns 60.13 % " "Info: Total interconnect delay = 2.004 ns ( 60.13 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "3.333 ns" { scir[2] scir~167 process0~21 Data_out[7]~8 Data_out[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.333 ns" { scir[2] scir~167 process0~21 Data_out[7]~8 Data_out[0]~reg0 } { 0.000ns 0.580ns 0.533ns 0.134ns 0.757ns } { 0.000ns 0.366ns 0.183ns 0.075ns 0.705ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.761 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { clk } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.542 ns) 2.761 ns Data_out\[0\]~reg0 2 REG LC_X44_Y23_N2 1 " "Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X44_Y23_N2; Fanout = 1; REG Node = 'Data_out\[0\]~reg0'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.036 ns" { clk Data_out[0]~reg0 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.89 % " "Info: Total cell delay = 1.267 ns ( 45.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns 54.11 % " "Info: Total interconnect delay = 1.494 ns ( 54.11 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk Data_out[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 Data_out[0]~reg0 } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.761 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "" { clk } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.542 ns) 2.761 ns scir\[2\] 2 REG LC_X41_Y23_N3 8 " "Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X41_Y23_N3; Fanout = 8; REG Node = 'scir\[2\]'" {  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.036 ns" { clk scir[2] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 83 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.89 % " "Info: Total cell delay = 1.267 ns ( 45.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns 54.11 % " "Info: Total interconnect delay = 1.494 ns ( 54.11 % )" {  } {  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk scir[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 scir[2] } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk Data_out[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 Data_out[0]~reg0 } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk scir[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 scir[2] } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 83 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "sci.vhd" "" { Text "E:/20036016_5/sci.vhd" 35 -1 0 } }  } 0}  } { { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "3.333 ns" { scir[2] scir~167 process0~21 Data_out[7]~8 Data_out[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.333 ns" { scir[2] scir~167 process0~21 Data_out[7]~8 Data_out[0]~reg0 } { 0.000ns 0.580ns 0.533ns 0.134ns 0.757ns } { 0.000ns 0.366ns 0.183ns 0.075ns 0.705ns } } } { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk Data_out[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 Data_out[0]~reg0 } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/20036016_5/db/sci_cmp.qrpt" "" { Report "E:/20036016_5/db/sci_cmp.qrpt" Compiler "sci" "UNKNOWN" "V1" "E:/20036016_5/db/sci.quartus_db" { Floorplan "E:/20036016_5/" "" "2.761 ns" { clk scir[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.761 ns" { clk clk~out0 scir[2] } { 0.000ns 0.000ns 1.494ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "wr " "Info: No valid register-to-register data paths exist for clock \"wr\"" {  } {  } 0}