total.tan.rpt

串口通信实验程序

; Total number of failed paths ;       ;               ;                                                ;                                                                          ;                                                                          ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPF10K20TI144-4    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_1MHz        ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; clk_1Hz         ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_1MHz'                                                                                                                                                                                                                                                                                                                                           ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                        ; To                                                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; sci:inst2|scir[1]                                                           ; sci:inst2|Data_out[6]                                                   ; clk_1MHz   ; clk_1MHz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; sci:inst2|scir[1]                                                           ; sci:inst2|Data_out[1]                                                   ; clk_1MHz   ; clk_1MHz ; None                        ; None                      ; 14.900 ns               ;
; N/A                                     ; 57.47 MHz ( period = 17.400 ns )                    ; sci:inst2|scir[4]                                                           ; sci:inst2|Data_out[6]                                                   ; clk_1MHz   ; clk_1MHz ; None                        ; None                      ; 13.800 ns               ;
; N/A                                     ; 57.47 MHz ( period = 17.400 ns )                    ; sci:inst2|scir[3]                                                           ; sci:inst2|Data_out[6]                                                   ; clk_1MHz   ; clk_1MHz ; None                        ; None                      ; 13.800 ns               ;
; N/A                                     ; 57.47 MHz ( period = 17.400 ns )                    ; sci:inst2|scir[2]                                                           ; sci:inst2|Data_out[6]                                                   ; clk_1MHz   ; clk_1MHz ; None                        ; None                      ; 13.800 ns               ;
; N/A                                     ; 57.47 MHz ( period = 17.400 ns )                    ; sci:inst2|scir[4]                                                           ; sci:inst2|Data_out[1]                                                   ; clk_1MHz   ; clk_1MHz ; None                        ; None                      ; 13.800 ns               ;