display_6_led.map.rpt

串口通信实验程序

+----------------------------------+-----------------+------------------------------------+---------------------------------+


+----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary  ;
+-----------------------------------+----------+
; Resource                          ; Usage    ;
+-----------------------------------+----------+
; Total logic elements              ; 75       ;
; Total combinational functions     ; 50       ;
;     -- Total 4-input functions    ; 18       ;
;     -- Total 3-input functions    ; 5        ;
;     -- Total 2-input functions    ; 3        ;
;     -- Total 1-input functions    ; 21       ;
;     -- Total 0-input functions    ; 3        ;
; Combinational cells for routing   ; 0        ;
; Total registers                   ; 53       ;
; Total logic cells in carry chains ; 20       ;
; I/O pins                          ; 17       ;
; Maximum fan-out node              ; clk_1MHz ;
; Maximum fan-out                   ; 38       ;
; Total fan-out                     ; 254      ;
; Average fan-out                   ; 2.76     ;
+-----------------------------------+----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------+
; |Block1                    ; 75 (2)      ; 53           ; 0           ; 0            ; 0       ; 0         ; 0         ; 17   ; 0            ; 22 (2)       ; 25 (0)            ; 28 (0)           ; 20 (0)          ; |Block1                     ;
;    |count8:inst|           ; 8 (8)       ; 8            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |Block1|count8:inst         ;
;    |display_6_led:inst3|   ; 21 (21)     ; 13           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 8 (8)        ; 2 (2)             ; 11 (11)          ; 6 (6)           ; |Block1|display_6_led:inst3 ;
;    |sci:inst2|             ; 44 (44)     ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 12 (12)      ; 23 (23)           ; 9 (9)            ; 6 (6)           ; |Block1|sci:inst2           ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 53    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 2     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 18    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |Block1|display_6_led:inst3|num[3] ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |Block1|sci:inst2|scir[1]          ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |Block1|sci:inst2|scir[2]          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/20036016_5/display_6_led.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jan 13 11:13:20 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off display_6_led -c display_6_led
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Found 2 design units, including 1 entities, in source file count26.vhd
    Info: Found design unit 1: count26-rtl
    Info: Found entity 1: count26
Info: Found 2 design units, including 1 entities, in source file count8.vhd
    Info: Found design unit 1: count8-rtl
    Info: Found entity 1: count8
Info: Found 2 design units, including 1 entities, in source file display_6_led.vhd
    Info: Found design unit 1: display_6_led-behave
    Info: Found entity 1: display_6_led
Info: Found 2 design units, including 1 entities, in source file sci.vhd
    Info: Found design unit 1: sci-rtl
    Info: Found entity 1: sci
Info: Found 1 design units, including 1 entities, in source file total.bdf
    Info: Found entity 1: total
Warning: Can't analyze file -- file E:/20036016_5/display_6_led.vhd is missing
Info: Elaborating entity "Block1" for the top level hierarchy
Info: Elaborating entity "display_6_led" for hierarchy "display_6_led:inst3"
Info: Elaborating entity "sci" for hierarchy "sci:inst2"
Warning: VHDL Process Statement warning at sci.vhd(69): signal "cs" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(134): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(135): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(136): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(137): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(138): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(139): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(140): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(141): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "count8" for hierarchy "count8:inst"
Info: Duplicate registers merged to single register
    Info: Duplicate register "sci:inst2|tdempty" merged to single register "sci:inst2|txdf"
Info: Duplicate registers merged to single register
    Info: Duplicate register "sci:inst2|din_latch[0]" merged to single register "count8:inst|q_out[0]", power-up level changed
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "DP" stuck at GND
Info: Implemented 92 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 14 output pins
    Info: Implemented 75 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Fri Jan 13 11:13:29 2006
    Info: Elapsed time: 00:00:10