sci.map.rpt

串口通信实验程序

; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |sci|scir[4]               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 6     ;
; Number of synthesis-generated cells                    ; 44    ;
; Number of WYSIWYG LUTs                                 ; 6     ;
; Number of synthesis-generated LUTs                     ; 20    ;
; Number of WYSIWYG registers                            ; 6     ;
; Number of synthesis-generated registers                ; 27    ;
; Number of cells with combinational logic only          ; 17    ;
; Number of cells with registers only                    ; 24    ;
; Number of cells with combinational logic and registers ; 9     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 33    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 16    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 26    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
sci


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |sci                       ; 50 (50)     ; 33           ; 0           ; 0            ; 0       ; 0         ; 0         ; 25   ; 0            ; 17 (17)      ; 24 (24)           ; 9 (9)            ; 6 (6)           ; |sci                ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/20036016_5/sci.map.eqn.


+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                            ;
+----------------------------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+
; sci.vhd                          ; yes             ; E:/20036016_5/sci.vhd        ;
+----------------------------------+-----------------+------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 50      ;
; Total combinational functions     ; 26      ;
; Total 4-input functions           ; 8       ;
; Total 3-input functions           ; 5       ;
; Total 2-input functions           ; 3       ;
; Total 1-input functions           ; 7       ;
; Total 0-input functions           ; 3       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 33      ;
; Total logic cells in carry chains ; 6       ;
; I/O pins                          ; 25      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 25      ;
; Total fan-out                     ; 187     ;
; Average fan-out                   ; 2.49    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Thu Jan 12 19:54:44 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off sci -c sci
Info: Found 2 design units, including 1 entities, in source file sci.vhd
    Info: Found design unit 1: sci-rtl
    Info: Found entity 1: sci
Warning: VHDL Signal Declaration warning at sci.vhd(23): ignored default value for signal "tdempty_s"
Warning: VHDL Signal Declaration warning at sci.vhd(24): ignored default value for signal "rdfull_s"
Warning: VHDL Process Statement warning at sci.vhd(69): signal "cs" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(134): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(135): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(136): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(137): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(138): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(139): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(140): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at sci.vhd(141): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Duplicate registers merged to single register
    Info: Duplicate register "tdempty_s" merged to single register "txdf"
Info: Implemented 75 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 11 output pins
    Info: Implemented 50 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Processing ended: Thu Jan 12 19:54:50 2006
    Info: Elapsed time: 00:00:06