count26.vhd

来自「串口通信实验程序」· VHDL 代码 · 共 29 行

--count26.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count26 is
  port(clkin: in std_logic;
       clkout:out std_logic);
end count26;
architecture rtl of count26 is
signal bcd1,bcd10:std_logic_vector(3 downto 0);
begin
    process(clkin)
    begin
      if clkin='1' and clkin'event then
            if bcd1="1001" then
               bcd10<=bcd10+'1';
               bcd1<="0000";
               clkout<='0';
            elsif bcd1="0101" and bcd10="0010" then
               bcd1<="0000";
               bcd10<="0000";
               clkout<='1';
            else
               bcd1<=bcd1+'1';
               clkout<='0';
            end if;
      end if;
    end process;
end rtl;