sci.vhd

串口通信实验程序

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;

Entity sci is
Port(clk,reset,rxd,rd,cs,wr:in std_logic;
      Txd,rdfull,tdempty:out std_logic;
      Data_in:in std_logic_vector( 7 downto 0);
      Data_out:out std_logic_vector( 7 downto 0));
End sci;

Architecture rtl of sci is
Signal scir:std_logic_vector(5 downto 0);
Signal sh_r:std_logic_vector(3 downto 0);
Signal sl_r:std_logic_vector(1 downto 0);
Signal scit:std_logic_vector(5 downto 0);
Signal sh_t:std_logic_vector(3 downto 0);
Signal sl_t:std_logic_vector(1 downto 0);
Signal d_fb:std_logic_vector(7 downto 0);
Signal din_latch:std_logic_vector(7 downto 0);
Signal rxdf:std_logic;
Signal txdf:std_logic;
Signal tdempty_s:std_logic:='1';
Signal rdfull_s:std_logic:='0';
Begin
sh_r<=scir(5 downto 2);
sl_r<=scir(1 downto 0);
sh_t<=scir(5 downto 2);
sl_t<=scir(1 downto 0);
tdempty<=tdempty_s;
rdfull<=rdfull_s;

Process(clk,rd,cs)
Begin
If rd='0'and cs='0' then
rdfull_s<='0';
Elsif clk'event and clk='1' then
If rxdf='1' and sh_r="1111" and sl_r="11" then
data_out<=d_fb;
rdfull_s<='1';
End if;
End if;
End process;


Process(wr,cs)
Begin
If wr'event and wr='1' then
If cs='0' then
din_latch<=data_in;
End if;
End if;
End process;


Process(clk)
Begin
if clk'event and clk='1' then
If rxd='0' then
rxdf<='1';
Elsif rxdf='1' and sh_r="1111" and sl_r="11"  then
rxdf<='0';
End if;
End if;
End process;

Process(clk,wr)
Begin
If  wr='0' and cs='0' then
txdf<='0';
tdempty_s<='0';
Elsif clk'event and clk='1' then
If (((txdf='0') and (sh_t="1111" )and (sl_t="11" ))or reset='0') then
tdempty_s<='1';
txdf<='1';
End if;
End if;
End process;


Process(clk,reset)
Begin
If  reset= '0' then
scir<="000000";
Elsif clk'event and clk='1' then
If scir<=27   and rxd='0'  then
scir<="011100";
Elsif scir<=27 and rxd='1' then
scir<="000000";
Else 
scir<=scir+1;
End if;
End if;
End process;


Process(clk,reset)
Begin
If reset='0' then
scit<="000000";
Elsif clk'event and clk='1' then
If scit<=27 then
If tdempty_s='0' and wr='1' then
Scit<="011100";
Else
Scit<="000000";
End if;
Else
Scit<=scit+1;
End if;
End if;
End process;


Process(clk,reset)
Begin
If reset='0' then
D_fb<="00000000";
Elsif clk'event and clk='1' then
If sh_r>="1000" and sh_r<="1111" and sl_r="01" then
D_fb(7)<=rxd;
For i in 0 to 6 loop
D_fb(i)<=d_fb(i+1); 
End loop;
End if;
End if;
End process;


Process(sh_t)
Begin
Case sh_t is
When "0111" => txd<='0';
When "1000" => txd<=din_latch(0);
When "1001" => txd<= din_latch(1);
When "1010" => txd<= din_latch(2);
When "1011" => txd<= din_latch(3);
When "1100" => txd<= din_latch(4);
When "1101" => txd<= din_latch(5);
When "1110" => txd<= din_latch(6);
When "1111" => txd<= din_latch(7);
When others=> txd<='1';
End case;
End process;
End rtl;