sci.tan.rpt

串口通信实验程序

; N/A           ; None        ; -2.676 ns ; cs         ; din_latch[6]     ; wr       ;
; N/A           ; None        ; -2.676 ns ; cs         ; din_latch[7]     ; wr       ;
; N/A           ; None        ; -2.676 ns ; cs         ; din_latch[5]     ; wr       ;
; N/A           ; None        ; -2.676 ns ; cs         ; din_latch[0]     ; wr       ;
; N/A           ; None        ; -2.676 ns ; cs         ; din_latch[1]     ; wr       ;
; N/A           ; None        ; -2.676 ns ; cs         ; din_latch[2]     ; wr       ;
; N/A           ; None        ; -2.835 ns ; rxd        ; d_fb[7]          ; clk      ;
; N/A           ; None        ; -2.930 ns ; rxd        ; rxdf             ; clk      ;
; N/A           ; None        ; -3.300 ns ; cs         ; Data_out[7]~reg0 ; clk      ;
; N/A           ; None        ; -3.300 ns ; cs         ; Data_out[6]~reg0 ; clk      ;
; N/A           ; None        ; -3.300 ns ; cs         ; Data_out[5]~reg0 ; clk      ;
; N/A           ; None        ; -3.300 ns ; cs         ; Data_out[4]~reg0 ; clk      ;
; N/A           ; None        ; -3.300 ns ; cs         ; Data_out[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.450 ns ; cs         ; Data_out[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.495 ns ; rd         ; Data_out[7]~reg0 ; clk      ;
; N/A           ; None        ; -3.495 ns ; rd         ; Data_out[6]~reg0 ; clk      ;
; N/A           ; None        ; -3.495 ns ; rd         ; Data_out[5]~reg0 ; clk      ;
; N/A           ; None        ; -3.495 ns ; rd         ; Data_out[4]~reg0 ; clk      ;
; N/A           ; None        ; -3.495 ns ; rd         ; Data_out[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.576 ns ; rxd        ; scir[2]          ; clk      ;
; N/A           ; None        ; -3.578 ns ; rxd        ; scir[3]          ; clk      ;
; N/A           ; None        ; -3.581 ns ; rxd        ; scir[4]          ; clk      ;
; N/A           ; None        ; -3.645 ns ; rd         ; Data_out[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.731 ns ; cs         ; Data_out[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.731 ns ; cs         ; Data_out[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.926 ns ; rd         ; Data_out[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.926 ns ; rd         ; Data_out[0]~reg0 ; clk      ;
+---------------+-------------+-----------+------------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Thu Jan 12 19:55:31 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off sci -c sci --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "wr" is an undefined clock
Info: Clock "clk" has Internal fmax of 285.8 MHz between source register "scir[2]" and destination register "Data_out[0]~reg0" (period= 3.499 ns)
    Info: + Longest register to register delay is 3.333 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y23_N3; Fanout = 8; REG Node = 'scir[2]'
        Info: 2: + IC(0.580 ns) + CELL(0.366 ns) = 0.946 ns; Loc. = LC_X40_Y23_N9; Fanout = 3; COMB Node = 'scir~167'
        Info: 3: + IC(0.533 ns) + CELL(0.183 ns) = 1.662 ns; Loc. = LC_X40_Y23_N6; Fanout = 3; COMB Node = 'process0~21'
        Info: 4: + IC(0.134 ns) + CELL(0.075 ns) = 1.871 ns; Loc. = LC_X40_Y23_N7; Fanout = 8; COMB Node = 'Data_out[7]~8'
        Info: 5: + IC(0.757 ns) + CELL(0.705 ns) = 3.333 ns; Loc. = LC_X44_Y23_N2; Fanout = 1; REG Node = 'Data_out[0]~reg0'
        Info: Total cell delay = 1.329 ns ( 39.87 % )
        Info: Total interconnect delay = 2.004 ns ( 60.13 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.761 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X44_Y23_N2; Fanout = 1; REG Node = 'Data_out[0]~reg0'
            Info: Total cell delay = 1.267 ns ( 45.89 % )
            Info: Total interconnect delay = 1.494 ns ( 54.11 % )
        Info: - Longest clock path from clock "clk" to source register is 2.761 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X41_Y23_N3; Fanout = 8; REG Node = 'scir[2]'
            Info: Total cell delay = 1.267 ns ( 45.89 % )
            Info: Total interconnect delay = 1.494 ns ( 54.11 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: No valid register-to-register data paths exist for clock "wr"
Info: tsu for register "Data_out[1]~reg0" (data pin = "rd", clock pin = "clk") is 4.036 ns
    Info: + Longest pin to register delay is 6.787 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_G8; Fanout = 2; PIN Node = 'rd'
        Info: 2: + IC(3.872 ns) + CELL(0.366 ns) = 5.325 ns; Loc. = LC_X40_Y23_N7; Fanout = 8; COMB Node = 'Data_out[7]~8'
        Info: 3: + IC(0.757 ns) + CELL(0.705 ns) = 6.787 ns; Loc. = LC_X44_Y23_N4; Fanout = 1; REG Node = 'Data_out[1]~reg0'
        Info: Total cell delay = 2.158 ns ( 31.80 % )
        Info: Total interconnect delay = 4.629 ns ( 68.20 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.761 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X44_Y23_N4; Fanout = 1; REG Node = 'Data_out[1]~reg0'
        Info: Total cell delay = 1.267 ns ( 45.89 % )
        Info: Total interconnect delay = 1.494 ns ( 54.11 % )
Info: tco from clock "clk" to destination pin "Txd" through register "scir[2]" is 10.324 ns
    Info: + Longest clock path from clock "clk" to source register is 2.761 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X41_Y23_N3; Fanout = 8; REG Node = 'scir[2]'
        Info: Total cell delay = 1.267 ns ( 45.89 % )
        Info: Total interconnect delay = 1.494 ns ( 54.11 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 7.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y23_N3; Fanout = 8; REG Node = 'scir[2]'
        Info: 2: + IC(1.038 ns) + CELL(0.366 ns) = 1.404 ns; Loc. = LC_X41_Y24_N1; Fanout = 1; COMB Node = 'Mux~41'
        Info: 3: + IC(0.310 ns) + CELL(0.280 ns) = 1.994 ns; Loc. = LC_X41_Y24_N8; Fanout = 1; COMB Node = 'Mux~42'
        Info: 4: + IC(0.327 ns) + CELL(0.366 ns) = 2.687 ns; Loc. = LC_X41_Y24_N3; Fanout = 1; COMB Node = 'Mux~160'
        Info: 5: + IC(0.495 ns) + CELL(0.366 ns) = 3.548 ns; Loc. = LC_X40_Y24_N2; Fanout = 1; COMB Node = 'Mux~161'
        Info: 6: + IC(1.455 ns) + CELL(2.404 ns) = 7.407 ns; Loc. = PIN_A6; Fanout = 0; PIN Node = 'Txd'
        Info: Total cell delay = 3.782 ns ( 51.06 % )
        Info: Total interconnect delay = 3.625 ns ( 48.94 % )
Info: th for register "txdf" (data pin = "reset", clock pin = "clk") is -0.951 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.761 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(1.494 ns) + CELL(0.542 ns) = 2.761 ns; Loc. = LC_X41_Y23_N0; Fanout = 1; REG Node = 'txdf'
        Info: Total cell delay = 1.267 ns ( 45.89 % )
        Info: Total interconnect delay = 1.494 ns ( 54.11 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 3.812 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 15; PIN Node = 'reset'
        Info: 2: + IC(1.873 ns) + CELL(0.183 ns) = 2.781 ns; Loc. = LC_X41_Y23_N7; Fanout = 1; COMB Node = 'rtl~1'
        Info: 3: + IC(0.326 ns) + CELL(0.705 ns) = 3.812 ns; Loc. = LC_X41_Y23_N0; Fanout = 1; REG Node = 'txdf'
        Info: Total cell delay = 1.613 ns ( 42.31 % )
        Info: Total interconnect delay = 2.199 ns ( 57.69 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jan 12 19:55:32 2006
    Info: Elapsed time: 00:00:02