clockdiv.vhd

来自「用vhdl实现占空比1：1的通用分频模块」· VHDL 代码 · 共 58 行

-- 占空比1：1的通用分频模块
-- by superdsp, 709th Research Institute.
-- Dec-7-2004
-- [e-mail]

library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;

entity ClockDiv is
generic (div_size: integer := 1);
port(
  clk : in std_logic;
  rst : in std_logic;
  clkout : out std_logic);
end ClockDiv; 

architecture behavioral of ClockDiv is
  signal c1 : integer range 0 to div_size - 1;
  signal c2 : integer range 0 to div_size - 1;
  signal div_even : std_logic;
  signal div_odd : std_logic;
begin

  process(rst, clk)
  begin
    if (rst = '0') then
      c1 <= 0;
    elsif rising_edge(clk) then
      if (c1 = div_size - 1) then
        c1 <= 0;
      else
        c1 <= c1 + 1;
      end if;
    end if;
  end process;

  process(rst, clk)
  begin
    if (rst = '0') then
      c2 <= 0;
    elsif falling_edge(clk) then
      if (c2 = div_size - 1) then
        c2 <= 0;
      else
        c2 <= c2 + 1;
      end if;
    end if;
  end process;

  div_even <= '1' when (c2 >= (div_size + 1) / 2) else '0';
  div_odd <= '1' when ((c2 >= (div_size + 1) / 2) or (c1 >= (div_size + 1) / 2)) else '0';

  clkout <= clk when (div_size = 1) else
            div_even when (div_size / 2 * 2 = div_size) else
            div_odd;

end behavioral;