fenpin10.rpt

工作原理： 脉冲输入

 (40)    18    B       DFFE   +  t        0      0   0    0    7    1   10  count1 (:60)
 (41)    17    B       TFFE   +  t        0      0   0    0    5    1   11  count0 (:61)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:     d:\0331smart_timerv10\7128slc-15\fenpin10.rpt
fenpin10

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC28 a
        | +--------------------- LC27 |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node1
        | | +------------------- LC26 |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node2
        | | | +----------------- LC25 |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node3
        | | | | +--------------- LC24 |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node4
        | | | | | +------------- LC23 |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node5
        | | | | | | +----------- LC22 count5
        | | | | | | | +--------- LC21 count4
        | | | | | | | | +------- LC20 count3
        | | | | | | | | | +----- LC19 count2
        | | | | | | | | | | +--- LC18 count1
        | | | | | | | | | | | +- LC17 count0
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC27 -> - - - - - - - - - - * - | - * | <-- |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node1
LC26 -> - - - - - - - - - * - - | - * | <-- |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node2
LC25 -> - - - - - - - - * - - - | - * | <-- |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node3
LC24 -> - - - - - - - * - - - - | - * | <-- |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node4
LC23 -> - - - - - - * - - - - - | - * | <-- |lpm_add_sub:65|addcore:adder|addcore:adder0|result_node5
LC22 -> * - - - - * * * * * * * | - * | <-- count5
LC21 -> * - - - * * * * * * * * | - * | <-- count4
LC20 -> * - - * * * * * * * * * | - * | <-- count3
LC19 -> * - * * * * * * * * * * | - * | <-- count2
LC18 -> * * * * * * * * * * * - | - * | <-- count1
LC17 -> * * * * * * * * * * * * | - * | <-- count0

Pin
43   -> - - - - - - - - - - - - | - - | <-- k


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:     d:\0331smart_timerv10\7128slc-15\fenpin10.rpt
fenpin10

** EQUATIONS **

k        : INPUT;

-- Node name is 'a' = ':63' 
-- Equation name is 'a', type is output 
 a       = TFFE( VCC, GLOBAL( k),  VCC,  VCC,  _EQ001);
  _EQ001 =  count3 &  count4 &  count5 &  _X001 &  _X002;
  _X001  = EXP(!count0 & !count2);
  _X002  = EXP(!count1 & !count2);

-- Node name is ':61' = 'count0' 
-- Equation name is 'count0', location is LC017, type is buried.
count0   = TFFE(!_EQ002, GLOBAL( k),  VCC,  VCC,  VCC);
  _EQ002 = !count0 &  count2 &  count3 &  count4 &  count5;

-- Node name is ':60' = 'count1' 
-- Equation name is 'count1', location is LC018, type is buried.
count1   = DFFE( _EQ003 $  _LC027, GLOBAL( k),  VCC,  VCC,  VCC);
  _EQ003 =  count0 &  count1 &  count3 &  count4 &  count5 &  _LC027
         #  count2 &  count3 &  count4 &  count5 &  _LC027;

-- Node name is ':59' = 'count2' 
-- Equation name is 'count2', location is LC019, type is buried.
count2   = DFFE( _EQ004 $  _LC026, GLOBAL( k),  VCC,  VCC,  VCC);
  _EQ004 =  count0 &  count1 &  count3 &  count4 &  count5 &  _LC026
         #  count2 &  count3 &  count4 &  count5 &  _LC026;

-- Node name is ':58' = 'count3' 
-- Equation name is 'count3', location is LC020, type is buried.
count3   = DFFE( _EQ005 $  _LC025, GLOBAL( k),  VCC,  VCC,  VCC);
  _EQ005 =  count0 &  count1 &  count3 &  count4 &  count5 &  _LC025
         #  count2 &  count3 &  count4 &  count5 &  _LC025;

-- Node name is ':57' = 'count4' 
-- Equation name is 'count4', location is LC021, type is buried.
count4   = DFFE( _EQ006 $  _LC024, GLOBAL( k),  VCC,  VCC,  VCC);
  _EQ006 =  count0 &  count1 &  count3 &  count4 &  count5 &  _LC024
         #  count2 &  count3 &  count4 &  count5 &  _LC024;

-- Node name is ':56' = 'count5' 
-- Equation name is 'count5', location is LC022, type is buried.
count5   = DFFE( _EQ007 $  _LC023, GLOBAL( k),  VCC,  VCC,  VCC);
  _EQ007 =  count0 &  count1 &  count3 &  count4 &  count5 &  _LC023
         #  count2 &  count3 &  count4 &  count5 &  _LC023;

-- Node name is '|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL(!count1 $ !count0);

-- Node name is '|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried 
_LC026   = LCELL( count2 $  _EQ008);
  _EQ008 =  count0 &  count1;

-- Node name is '|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( count3 $  _EQ009);
  _EQ009 =  count0 &  count1 &  count2;

-- Node name is '|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( count4 $  _EQ010);
  _EQ010 =  count0 &  count1 &  count2 &  count3;

-- Node name is '|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( count5 $  _EQ011);
  _EQ011 =  count0 &  count1 &  count2 &  count3 &  count4;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information              d:\0331smart_timerv10\7128slc-15\fenpin10.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,919K