📄 addr_chose.rpt
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_X008 = EXP( addr0 & !addr1 & addr2 & f2);
_X009 = EXP(!addr0 & addr1 & !addr2 & c2);
_X010 = EXP(!addr0 & !addr1 & addr2 & e2);
_X011 = EXP( addr0 & !addr1 & !addr2 & b2);
_X012 = EXP(!addr0 & !addr1 & !addr2 & _LC038);
-- Node name is '~155~1'
-- Equation name is '~155~1', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ020 $ VCC);
_EQ020 = _X013 & _X014 & _X015 & _X016 & _X017 & _X018 & _X019 &
_X020;
_X013 = EXP( addr0 & addr1 & !addr2 & d1);
_X014 = EXP( addr0 & addr1 & addr2 & _LC037);
_X015 = EXP(!addr0 & addr1 & addr2 & g1);
_X016 = EXP( addr0 & !addr1 & addr2 & f1);
_X017 = EXP(!addr0 & addr1 & !addr2 & c1);
_X018 = EXP(!addr0 & !addr1 & addr2 & e1);
_X019 = EXP( addr0 & !addr1 & !addr2 & b1);
_X020 = EXP(!addr0 & !addr1 & !addr2 & _LC037);
-- Node name is '~156~1'
-- Equation name is '~156~1', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ021 $ VCC);
_EQ021 = _X021 & _X022 & _X023 & _X024 & _X025 & _X026 & _X027 &
_X028;
_X021 = EXP( addr0 & addr1 & !addr2 & d0);
_X022 = EXP( addr0 & addr1 & addr2 & _LC036);
_X023 = EXP(!addr0 & addr1 & addr2 & g0);
_X024 = EXP( addr0 & !addr1 & addr2 & f0);
_X025 = EXP(!addr0 & addr1 & !addr2 & c0);
_X026 = EXP(!addr0 & !addr1 & addr2 & e0);
_X027 = EXP( addr0 & !addr1 & !addr2 & b0);
_X028 = EXP(!addr0 & !addr1 & !addr2 & _LC036);
-- Node name is '~161~1'
-- Equation name is '~161~1', location is LC041, type is buried.
-- synthesized logic cell
_LC041 = LCELL( _EQ022 $ _LC047);
_EQ022 = !addr0 & !addr1 & !addr2 & a3 & !_LC040 & _X002 & _X003 &
_X004
# !addr0 & !addr1 & !addr2 & !a3 & _LC047;
_X002 = EXP(!addr0 & !addr1 & addr2 & e3);
_X003 = EXP( addr0 & !addr1 & !addr2 & b3);
_X004 = EXP(!addr0 & !addr1 & !addr2 & _LC041);
-- Node name is '~161~2'
-- Equation name is '~161~2', location is LC040, type is buried.
-- synthesized logic cell
_LC040 = LCELL( _EQ023 $ GND);
_EQ023 = addr0 & addr1 & addr2 & _LC041
# addr0 & addr1 & !addr2 & d3
# !addr0 & addr1 & addr2 & g3
# addr0 & !addr1 & addr2 & f3
# !addr0 & addr1 & !addr2 & c3;
-- Node name is '~162~1'
-- Equation name is '~162~1', location is LC038, type is buried.
-- synthesized logic cell
_LC038 = LCELL( _EQ024 $ GND);
_EQ024 = !addr0 & !addr1 & !addr2 & a2
# _LC058 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is '~163~1'
-- Equation name is '~163~1', location is LC037, type is buried.
-- synthesized logic cell
_LC037 = LCELL( _EQ025 $ GND);
_EQ025 = !addr0 & !addr1 & !addr2 & a1
# _LC024 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is '~164~1'
-- Equation name is '~164~1', location is LC036, type is buried.
-- synthesized logic cell
_LC036 = LCELL( _EQ026 $ GND);
_EQ026 = !addr0 & !addr1 & !addr2 & a0
# _LC021 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is '~292~1'
-- Equation name is '~292~1', location is LC049, type is buried.
-- synthesized logic cell
_LC049 = LCELL( _EQ027 $ VCC);
_EQ027 = !addr0 & !addr1 & !addr2 & !_LC050
# addr1 & addr2 & !_LC050
# !addr0 & addr1 & addr2;
-- Node name is '~293~1'
-- Equation name is '~293~1', location is LC035, type is buried.
-- synthesized logic cell
_LC035 = LCELL( _EQ028 $ VCC);
_EQ028 = !addr0 & !addr1 & !addr2 & !_LC051
# addr0 & addr2 & !_LC051
# addr0 & !addr1 & addr2;
-- Node name is '~294~1'
-- Equation name is '~294~1', location is LC033, type is buried.
-- synthesized logic cell
_LC033 = LCELL( _EQ029 $ VCC);
_EQ029 = addr0 & addr1 & addr2 & !_LC052
# !addr0 & !addr1 & addr2
# !addr0 & !addr1 & !_LC052;
-- Node name is '~295~1'
-- Equation name is '~295~1', location is LC044, type is buried.
-- synthesized logic cell
_LC044 = LCELL( _EQ030 $ VCC);
_EQ030 = !addr0 & !addr1 & !addr2 & !_LC053
# addr0 & addr1 & !_LC053
# addr0 & addr1 & !addr2;
-- Node name is '~296~1'
-- Equation name is '~296~1', location is LC045, type is buried.
-- synthesized logic cell
_LC045 = LCELL( _EQ031 $ VCC);
_EQ031 = addr0 & addr1 & addr2 & !_LC054
# !addr0 & addr1 & !addr2
# !addr0 & !addr2 & !_LC054;
-- Node name is '~297~1'
-- Equation name is '~297~1', location is LC048, type is buried.
-- synthesized logic cell
_LC048 = LCELL( _EQ032 $ VCC);
_EQ032 = addr0 & addr1 & addr2 & !_LC056
# addr0 & !addr1 & !addr2
# !addr1 & !addr2 & !_LC056;
-- Node name is '~298~1'
-- Equation name is '~298~1', location is LC034, type is buried.
-- synthesized logic cell
_LC034 = LCELL( _EQ033 $ VCC);
_EQ033 = addr0 & addr1 & addr2 & !_LC057
# !addr0 & !addr1 & !addr2 & !_LC057;
-- Node name is '~306~1'
-- Equation name is '~306~1', location is LC050, type is buried.
-- synthesized logic cell
_LC050 = LCELL( _EQ034 $ VCC);
_EQ034 = !_LC049 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is '~307~1'
-- Equation name is '~307~1', location is LC051, type is buried.
-- synthesized logic cell
_LC051 = LCELL( _EQ035 $ VCC);
_EQ035 = !_LC035 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is '~308~1'
-- Equation name is '~308~1', location is LC052, type is buried.
-- synthesized logic cell
_LC052 = LCELL( _EQ036 $ VCC);
_EQ036 = !_LC033 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is '~309~1'
-- Equation name is '~309~1', location is LC053, type is buried.
-- synthesized logic cell
_LC053 = LCELL( _EQ037 $ VCC);
_EQ037 = !_LC044 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is '~310~1'
-- Equation name is '~310~1', location is LC054, type is buried.
-- synthesized logic cell
_LC054 = LCELL( _EQ038 $ VCC);
_EQ038 = !_LC045 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is '~311~1'
-- Equation name is '~311~1', location is LC056, type is buried.
-- synthesized logic cell
_LC056 = LCELL( _EQ039 $ VCC);
_EQ039 = !_LC048 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is '~312~1'
-- Equation name is '~312~1', location is LC057, type is buried.
-- synthesized logic cell
_LC057 = LCELL( _EQ040 $ GND);
_EQ040 = _LC034 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs C, D
Project Information d:\rest_1\res_3\addr_chose.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,211K
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