📄 addr_chose.rpt
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addr_chose
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--- LC24 ~155~1
| +- LC21 ~156~1
| |
| | Other LABs fed by signals
| | that feed LAB 'B'
LC | | | A B C D | Logic cells that feed LAB 'B':
Pin
22 -> * * | - * * * | <-- addr0
20 -> * * | - * * * | <-- addr1
21 -> * * | - * * * | <-- addr2
44 -> - * | - * - - | <-- b0
45 -> * - | - * - - | <-- b1
33 -> - * | - * - - | <-- c0
34 -> * - | - * - - | <-- c1
39 -> - * | - * - - | <-- d0
28 -> * - | - * - - | <-- d1
12 -> - * | - * - - | <-- e0
15 -> * - | - * - - | <-- e1
18 -> - * | - * - - | <-- f0
11 -> * - | - * - - | <-- f1
8 -> - * | - * - - | <-- g0
6 -> * - | - * - - | <-- g1
LC37 -> * - | - * - - | <-- ~163~1
LC36 -> - * | - * - - | <-- ~164~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\rest_1\res_3\addr_chose.rpt
addr_chose
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC39 outio0
| +----------------------------- LC42 outio1
| | +--------------------------- LC43 outio2
| | | +------------------------- LC46 outio3
| | | | +----------------------- LC47 ~153~1
| | | | | +--------------------- LC41 ~161~1
| | | | | | +------------------- LC40 ~161~2
| | | | | | | +----------------- LC38 ~162~1
| | | | | | | | +--------------- LC37 ~163~1
| | | | | | | | | +------------- LC36 ~164~1
| | | | | | | | | | +----------- LC35 ~293~1
| | | | | | | | | | | +--------- LC33 ~294~1
| | | | | | | | | | | | +------- LC44 ~295~1
| | | | | | | | | | | | | +----- LC45 ~296~1
| | | | | | | | | | | | | | +--- LC48 ~297~1
| | | | | | | | | | | | | | | +- LC34 ~298~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC47 -> - - - * - * - - - - - - - - - - | - - * - | <-- ~153~1
LC41 -> - - - - * * * - - - - - - - - - | - - * - | <-- ~161~1
LC40 -> - - - - * * - - - - - - - - - - | - - * - | <-- ~161~2
Pin
22 -> * * * * * * * * * * * * * * * * | - * * * | <-- addr0
20 -> * * * * * * * * * * * * * * * * | - * * * | <-- addr1
21 -> * * * * * * * * * * * * * * * * | - * * * | <-- addr2
30 -> * - - - - - - - - * - - - - - - | - - * - | <-- a0
31 -> - * - - - - - - * - - - - - - - | - - * - | <-- a1
27 -> - - * - - - - * - - - - - - - - | - - * - | <-- a2
25 -> - - - * - * - - - - - - - - - - | - - * - | <-- a3
29 -> - - - - * * - - - - - - - - - - | - - * - | <-- b3
37 -> - - - - - - * - - - - - - - - - | - - * - | <-- c3
40 -> - - - - - - * - - - - - - - - - | - - * - | <-- d3
17 -> - - - - * * - - - - - - - - - - | - - * - | <-- e3
9 -> - - - - - - * - - - - - - - - - | - - * - | <-- f3
4 -> - - - - - - * - - - - - - - - - | - - * - | <-- g3
LC58 -> - - * - - - - * - - - - - - - - | - - * - | <-- ~154~1
LC24 -> - * - - - - - - * - - - - - - - | - - * - | <-- ~155~1
LC21 -> * - - - - - - - - * - - - - - - | - - * - | <-- ~156~1
LC51 -> - - - - - - - - - - * - - - - - | - - * - | <-- ~307~1
LC52 -> - - - - - - - - - - - * - - - - | - - * - | <-- ~308~1
LC53 -> - - - - - - - - - - - - * - - - | - - * - | <-- ~309~1
LC54 -> - - - - - - - - - - - - - * - - | - - * - | <-- ~310~1
LC56 -> - - - - - - - - - - - - - - * - | - - * - | <-- ~311~1
LC57 -> - - - - - - - - - - - - - - - * | - - * - | <-- ~312~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\rest_1\res_3\addr_chose.rpt
addr_chose
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC62 wei0
| +----------------------------- LC55 wei1
| | +--------------------------- LC59 wei2
| | | +------------------------- LC60 wei3
| | | | +----------------------- LC61 wei4
| | | | | +--------------------- LC63 wei5
| | | | | | +------------------- LC64 wei6
| | | | | | | +----------------- LC58 ~154~1
| | | | | | | | +--------------- LC49 ~292~1
| | | | | | | | | +------------- LC50 ~306~1
| | | | | | | | | | +----------- LC51 ~307~1
| | | | | | | | | | | +--------- LC52 ~308~1
| | | | | | | | | | | | +------- LC53 ~309~1
| | | | | | | | | | | | | +----- LC54 ~310~1
| | | | | | | | | | | | | | +--- LC56 ~311~1
| | | | | | | | | | | | | | | +- LC57 ~312~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC49 -> - - - - - - * - - * - - - - - - | - - - * | <-- ~292~1
LC50 -> - - - - - - - - * - - - - - - - | - - - * | <-- ~306~1
Pin
22 -> * * * * * * * * * * * * * * * * | - * * * | <-- addr0
20 -> * * * * * * * * * * * * * * * * | - * * * | <-- addr1
21 -> * * * * * * * * * * * * * * * * | - * * * | <-- addr2
41 -> - - - - - - - * - - - - - - - - | - - - * | <-- b2
36 -> - - - - - - - * - - - - - - - - | - - - * | <-- c2
35 -> - - - - - - - * - - - - - - - - | - - - * | <-- d2
16 -> - - - - - - - * - - - - - - - - | - - - * | <-- e2
10 -> - - - - - - - * - - - - - - - - | - - - * | <-- f2
5 -> - - - - - - - * - - - - - - - - | - - - * | <-- g2
LC38 -> - - - - - - - * - - - - - - - - | - - - * | <-- ~162~1
LC35 -> - - - - - * - - - - * - - - - - | - - - * | <-- ~293~1
LC33 -> - - - - * - - - - - - * - - - - | - - - * | <-- ~294~1
LC44 -> - - - * - - - - - - - - * - - - | - - - * | <-- ~295~1
LC45 -> - - * - - - - - - - - - - * - - | - - - * | <-- ~296~1
LC48 -> - * - - - - - - - - - - - - * - | - - - * | <-- ~297~1
LC34 -> * - - - - - - - - - - - - - - * | - - - * | <-- ~298~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\rest_1\res_3\addr_chose.rpt
addr_chose
** EQUATIONS **
addr0 : INPUT;
addr1 : INPUT;
addr2 : INPUT;
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
c0 : INPUT;
c1 : INPUT;
c2 : INPUT;
c3 : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
e0 : INPUT;
e1 : INPUT;
e2 : INPUT;
e3 : INPUT;
f0 : INPUT;
f1 : INPUT;
f2 : INPUT;
f3 : INPUT;
g0 : INPUT;
g1 : INPUT;
g2 : INPUT;
g3 : INPUT;
-- Node name is 'outio0'
-- Equation name is 'outio0', location is LC039, type is output.
outio0 = LCELL( _EQ001 $ GND);
_EQ001 = !addr0 & !addr1 & !addr2 & a0
# _LC021 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is 'outio1'
-- Equation name is 'outio1', location is LC042, type is output.
outio1 = LCELL( _EQ002 $ GND);
_EQ002 = !addr0 & !addr1 & !addr2 & a1
# _LC024 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is 'outio2'
-- Equation name is 'outio2', location is LC043, type is output.
outio2 = LCELL( _EQ003 $ GND);
_EQ003 = !addr0 & !addr1 & !addr2 & a2
# _LC058 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is 'outio3'
-- Equation name is 'outio3', location is LC046, type is output.
outio3 = LCELL( _EQ004 $ GND);
_EQ004 = !addr0 & !addr1 & !addr2 & a3
# _LC047 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is 'wei0'
-- Equation name is 'wei0', location is LC062, type is output.
wei0 = LCELL( _EQ005 $ GND);
_EQ005 = _LC034 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
-- Node name is 'wei1'
-- Equation name is 'wei1', location is LC055, type is output.
wei1 = LCELL( _EQ006 $ _EQ007);
_EQ006 = _LC048 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
_EQ007 = !addr0 & !addr1 & !addr2;
-- Node name is 'wei2'
-- Equation name is 'wei2', location is LC059, type is output.
wei2 = LCELL( _EQ008 $ _EQ009);
_EQ008 = _LC045 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
_EQ009 = !addr0 & !addr1 & !addr2;
-- Node name is 'wei3'
-- Equation name is 'wei3', location is LC060, type is output.
wei3 = LCELL( _EQ010 $ _EQ011);
_EQ010 = _LC044 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
_EQ011 = !addr0 & !addr1 & !addr2;
-- Node name is 'wei4'
-- Equation name is 'wei4', location is LC061, type is output.
wei4 = LCELL( _EQ012 $ _EQ013);
_EQ012 = _LC033 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
_EQ013 = !addr0 & !addr1 & !addr2;
-- Node name is 'wei5'
-- Equation name is 'wei5', location is LC063, type is output.
wei5 = LCELL( _EQ014 $ _EQ015);
_EQ014 = _LC035 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
_EQ015 = !addr0 & !addr1 & !addr2;
-- Node name is 'wei6'
-- Equation name is 'wei6', location is LC064, type is output.
wei6 = LCELL( _EQ016 $ _EQ017);
_EQ016 = _LC049 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2);
_EQ017 = !addr0 & !addr1 & !addr2;
-- Node name is '~153~1'
-- Equation name is '~153~1', location is LC047, type is buried.
-- synthesized logic cell
_LC047 = LCELL( _EQ018 $ VCC);
_EQ018 = !_LC040 & _X002 & _X003 & _X004;
_X002 = EXP(!addr0 & !addr1 & addr2 & e3);
_X003 = EXP( addr0 & !addr1 & !addr2 & b3);
_X004 = EXP(!addr0 & !addr1 & !addr2 & _LC041);
-- Node name is '~154~1'
-- Equation name is '~154~1', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ019 $ VCC);
_EQ019 = _X005 & _X006 & _X007 & _X008 & _X009 & _X010 & _X011 &
_X012;
_X005 = EXP( addr0 & addr1 & !addr2 & d2);
_X006 = EXP( addr0 & addr1 & addr2 & _LC038);
_X007 = EXP(!addr0 & addr1 & addr2 & g2);
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