📄 addr_chose.rpt
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Project Information d:\rest_1\res_3\addr_chose.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/01/2005 17:32:05
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
addr_chose
EPM7064SLC84-5 31 11 0 34 29 53 %
User Pins: 31 11 0
Device-Specific Information: d:\rest_1\res_3\addr_chose.rpt
addr_chose
***** Logic for device 'addr_chose' compiled without errors.
Device: EPM7064SLC84-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
V
C V
C w w w C w w w
G I G G G G G e e e C e e e
f f f g N g g g N N N N N N i i i I i i i
1 2 3 0 D 1 2 3 T D D D D D 6 5 0 O 4 3 2
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
e0 | 12 74 | RESERVED
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
e1 | 15 71 | #TDO
e2 | 16 70 | wei1
e3 | 17 69 | RESERVED
f0 | 18 68 | RESERVED
GND | 19 67 | RESERVED
addr1 | 20 66 | VCCIO
addr2 | 21 65 | RESERVED
addr0 | 22 EPM7064SLC84-5 64 | RESERVED
#TMS | 23 63 | RESERVED
RESERVED | 24 62 | #TCK
a3 | 25 61 | RESERVED
VCCIO | 26 60 | outio3
a2 | 27 59 | GND
d1 | 28 58 | RESERVED
b3 | 29 57 | RESERVED
a0 | 30 56 | outio2
a1 | 31 55 | outio1
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
c c d c c V d d b G V b b R G R R R o R V
0 1 2 2 3 C 0 3 2 N C 0 1 E N E E E u E C
C D C S D S S S t S C
I I E E E E i E I
O N R R R R o R O
T V V V V 0 V
E E E E E
D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\rest_1\res_3\addr_chose.rpt
addr_chose
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 2/16( 12%) 15/16( 93%) 16/16(100%) 17/36( 47%)
C: LC33 - LC48 16/16(100%) 7/16( 43%) 5/16( 31%) 25/36( 69%)
D: LC49 - LC64 16/16(100%) 8/16( 50%) 9/16( 56%) 18/36( 50%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 46/64 ( 71%)
Total logic cells used: 34/64 ( 53%)
Total shareable expanders used: 29/64 ( 45%)
Total Turbo logic cells used: 34/64 ( 53%)
Total shareable expanders not available (n/a): 1/64 ( 1%)
Average fan-in: 5.08
Total fan-in: 173
Total input pins required: 31
Total fast input logic cells required: 0
Total output pins required: 11
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 34
Total flipflops required: 0
Total product terms required: 95
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 28
Synthesized logic cells: 23/ 64 ( 35%)
Device-Specific Information: d:\rest_1\res_3\addr_chose.rpt
addr_chose
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
22 (1) (A) INPUT 0 0 0 0 0 11 23 addr0
20 (3) (A) INPUT 0 0 0 0 0 11 23 addr1
21 (2) (A) INPUT 0 0 0 0 0 11 23 addr2
30 (26) (B) INPUT 0 0 0 0 0 1 1 a0
31 (25) (B) INPUT 0 0 0 0 0 1 1 a1
27 (29) (B) INPUT 0 0 0 0 0 1 1 a2
25 (30) (B) INPUT 0 0 0 0 0 1 1 a3
44 (33) (C) INPUT 0 0 0 0 0 0 1 b0
45 (34) (C) INPUT 0 0 0 0 0 0 1 b1
41 (17) (B) INPUT 0 0 0 0 0 0 1 b2
29 (27) (B) INPUT 0 0 0 0 0 0 2 b3
33 (24) (B) INPUT 0 0 0 0 0 0 1 c0
34 (23) (B) INPUT 0 0 0 0 0 0 1 c1
36 (21) (B) INPUT 0 0 0 0 0 0 1 c2
37 (20) (B) INPUT 0 0 0 0 0 0 1 c3
39 (19) (B) INPUT 0 0 0 0 0 0 1 d0
28 (28) (B) INPUT 0 0 0 0 0 0 1 d1
35 (22) (B) INPUT 0 0 0 0 0 0 1 d2
40 (18) (B) INPUT 0 0 0 0 0 0 1 d3
12 (9) (A) INPUT 0 0 0 0 0 0 1 e0
15 (7) (A) INPUT 0 0 0 0 0 0 1 e1
16 (6) (A) INPUT 0 0 0 0 0 0 1 e2
17 (5) (A) INPUT 0 0 0 0 0 0 2 e3
18 (4) (A) INPUT 0 0 0 0 0 0 1 f0
11 (10) (A) INPUT 0 0 0 0 0 0 1 f1
10 (11) (A) INPUT 0 0 0 0 0 0 1 f2
9 (12) (A) INPUT 0 0 0 0 0 0 1 f3
8 (13) (A) INPUT 0 0 0 0 0 0 1 g0
6 (14) (A) INPUT 0 0 0 0 0 0 1 g1
5 (15) (A) INPUT 0 0 0 0 0 0 1 g2
4 (16) (A) INPUT 0 0 0 0 0 0 1 g3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\rest_1\res_3\addr_chose.rpt
addr_chose
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
51 39 C OUTPUT t 1 1 0 4 1 0 0 outio0
55 42 C OUTPUT t 1 1 0 4 1 0 0 outio1
56 43 C OUTPUT t 1 1 0 4 1 0 0 outio2
60 46 C OUTPUT t 1 1 0 4 1 0 0 outio3
79 62 D OUTPUT t 1 1 0 3 1 0 0 wei0
70 55 D OUTPUT t 1 1 0 3 1 0 0 wei1
75 59 D OUTPUT t 1 1 0 3 1 0 0 wei2
76 60 D OUTPUT t 1 1 0 3 1 0 0 wei3
77 61 D OUTPUT t 1 1 0 3 1 0 0 wei4
80 63 D OUTPUT t 1 1 0 3 1 0 0 wei5
81 64 D OUTPUT t 1 1 0 3 1 0 0 wei6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\rest_1\res_3\addr_chose.rpt
addr_chose
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(61) 47 C SOFT s t 3 3 0 5 2 1 1 ~153~1
(74) 58 D SOFT s t 8 0 0 9 1 1 1 ~154~1
(33) 24 B SOFT s t 8 0 0 9 1 1 1 ~155~1
(36) 21 B SOFT s t 8 0 0 9 1 1 1 ~156~1
(54) 41 C LCELL s t 3 3 0 6 3 0 3 ~161~1
(52) 40 C SOFT s t 1 0 1 7 1 0 2 ~161~2
(50) 38 C LCELL s t 1 1 0 4 1 0 1 ~162~1
(49) 37 C LCELL s t 1 1 0 4 1 0 1 ~163~1
(48) 36 C LCELL s t 1 1 0 4 1 0 1 ~164~1
(63) 49 D SOFT s t 0 0 0 3 1 1 1 ~292~1
(46) 35 C SOFT s t 0 0 0 3 1 1 1 ~293~1
(44) 33 C SOFT s t 0 0 0 3 1 1 1 ~294~1
(57) 44 C SOFT s t 0 0 0 3 1 1 1 ~295~1
(58) 45 C SOFT s t 0 0 0 3 1 1 1 ~296~1
(62) 48 C SOFT s t 0 0 0 3 1 1 1 ~297~1
(45) 34 C SOFT s t 0 0 0 3 1 1 1 ~298~1
(64) 50 D LCELL s t 1 1 0 3 1 0 1 ~306~1
(65) 51 D LCELL s t 1 1 0 3 1 0 1 ~307~1
(67) 52 D LCELL s t 1 1 0 3 1 0 1 ~308~1
(68) 53 D LCELL s t 1 1 0 3 1 0 1 ~309~1
(69) 54 D LCELL s t 1 1 0 3 1 0 1 ~310~1
(71) 56 D LCELL s t 1 1 0 3 1 0 1 ~311~1
(73) 57 D LCELL s t 1 1 0 3 1 0 1 ~312~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\rest_1\res_3\addr_chose.rpt
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