📄 sellmachine.rpt
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Device-Specific Information: d:\dspexperiment\eda\sellmachine.rpt
sellmachine
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
1 (3) (A) INPUT 0 0 0 0 0 0 1 A1
99 (6) (A) INPUT 0 0 0 0 0 0 1 A4
98 (8) (A) INPUT 0 0 0 0 0 0 1 A8
87 - - INPUT G 0 0 0 0 0 0 0 CANCEL
90 - - INPUT G 0 0 0 0 0 0 0 CLK1K
96 (11) (A) INPUT 0 0 0 0 0 0 1 COIN1
97 (9) (A) INPUT 0 0 0 0 0 0 1 COIN2
100 (5) (A) INPUT 0 0 0 0 0 0 1 COIN5
2 (1) (A) INPUT 0 0 0 0 0 0 15 START
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
h = Register powers up high
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\dspexperiment\eda\sellmachine.rpt
sellmachine
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
35 53 D OUTPUT t 3 2 0 0 13 0 0 LAMP0
64 99 G OUTPUT t 3 2 0 0 13 0 0 LAMP1
79 120 H OUTPUT t 2 1 0 0 12 0 0 LAMP2
81 123 H OUTPUT t 0 0 0 0 8 0 0 LAMP3
75 113 H OUTPUT t 0 0 0 0 6 0 0 OUTA1
76 115 H OUTPUT t 0 0 0 0 4 0 0 OUTA4
77 117 H OUTPUT t 0 0 0 0 3 0 0 OUTA8
78 118 H OUTPUT t 0 0 0 0 6 0 0 REJECTA
80 121 H OUTPUT t 14 0 0 0 24 0 0 REJECTCOIN
44 70 E FF t 12 0 1 0 14 5 4 TEST0
45 72 E FF t 1 0 1 0 10 4 4 TEST1
40 65 E FF t 1 0 1 0 11 3 4 TEST2
41 67 E FF t 1 0 1 0 12 2 4 TEST3
46 73 E FF t 1 0 1 0 13 1 4 TEST4
84 126 H OUTPUT t 0 0 0 0 0 0 0 TEST5
85 128 H OUTPUT t 0 0 0 0 0 0 0 TEST6
83 125 H OUTPUT t 0 0 0 0 0 0 0 TEST7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
h = Register powers up high
Device-Specific Information: d:\dspexperiment\eda\sellmachine.rpt
sellmachine
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(8) 25 B TFFE t 0 0 0 0 3 5 0 CLK1S
- 122 H DFFE + t 0 0 0 0 1 0 1 |lpm_compare:103|comptree:comparator|cmpchain:cmp_end|aeb_out
(61) 94 F DFFE + t 0 0 0 0 4 0 1 |lpm_compare:103|comptree:comparator|cmpchain:cmp0|aeb_out
- 92 F DFFE + t 0 0 0 0 4 0 1 |lpm_compare:103|comptree:comparator|cmpchain:cmp1|aeb_out
(99) 6 A DFFE + t 0 0 0 0 2 0 4 |lpm_compare:319|comptree:comparator|cmpchain:cmp_end|aeb_out
- 4 A DFFE + t 0 0 0 0 2 0 4 |lpm_compare:411|comptree:comparator|cmpchain:cmp_end|aeb_out
(2) 1 A DFFE + t 0 0 0 0 2 0 4 |lpm_compare:503|comptree:comparator|cmpchain:cmp_end|aeb_out
(54) 85 F TFFE + t 0 0 0 0 9 0 10 |lpm_counter:53|dffs0
- 84 F TFFE + t 0 0 0 0 1 0 9 |lpm_counter:53|dffs1
(53) 83 F TFFE + t 0 0 0 0 2 0 8 |lpm_counter:53|dffs2
(60) 93 F TFFE + t 0 0 0 0 9 0 8 |lpm_counter:53|dffs3
- 95 F TFFE + t 0 0 0 0 4 0 7 |lpm_counter:53|dffs4
(58) 91 F TFFE + t 0 0 0 0 5 0 6 |lpm_counter:53|dffs5
- 90 F TFFE + t 0 0 0 0 6 0 5 |lpm_counter:53|dffs6
(57) 89 F TFFE + t 0 0 0 0 7 0 4 |lpm_counter:53|dffs7
- 82 F TFFE + t 0 0 0 0 8 0 3 |lpm_counter:53|dffs8
(29) 61 D TFFE + t 3 3 0 0 8 12 16 |lpm_counter:133|dffs0
(30) 59 D TFFE + t 3 3 0 0 8 12 16 |lpm_counter:133|dffs1
- 58 D TFFE + t 3 3 0 0 8 12 16 |lpm_counter:169|dffs0
- 52 D TFFE + t 3 3 0 0 8 12 16 |lpm_counter:169|dffs1
(36) 51 D TFFE + t 3 3 0 0 8 11 16 |lpm_counter:205|dffs0
- 50 D TFFE + t 3 3 0 0 8 11 16 |lpm_counter:205|dffs1
(97) 9 A DFFE + t 1 1 0 0 4 0 3 |lpm_counter:283|dffs0
- 10 A TFFE + t 1 1 0 0 4 0 3 |lpm_counter:283|dffs1
(25) 33 C TFFE t 0 0 0 0 3 0 21 |lpm_counter:335|dffs0
(24) 35 C TFFE t 0 0 0 0 4 0 6 |lpm_counter:335|dffs1
- 34 C TFFE t 0 0 0 0 5 0 3 |lpm_counter:335|dffs2
(15) 48 C TFFE t 0 0 0 0 6 0 1 |lpm_counter:335|dffs3
(93) 14 A DFFE + t 1 1 0 0 4 0 3 |lpm_counter:375|dffs0
- 12 A TFFE + t 1 1 0 0 4 0 3 |lpm_counter:375|dffs1
(20) 41 C TFFE t 0 0 0 0 3 0 9 |lpm_counter:427|dffs0
- 47 C TFFE t 0 0 0 0 4 0 7 |lpm_counter:427|dffs1
(16) 46 C TFFE t 0 0 0 0 5 0 5 |lpm_counter:427|dffs2
(17) 45 C TFFE t 0 0 0 0 6 0 2 |lpm_counter:427|dffs3
(94) 13 A DFFE + t 1 1 0 0 4 0 3 |lpm_counter:467|dffs0
(96) 11 A TFFE + t 1 1 0 0 4 0 3 |lpm_counter:467|dffs1
(6) 29 B TFFE t 0 0 0 0 3 0 22 |lpm_counter:519|dffs0
(5) 30 B TFFE t 0 0 0 0 4 0 16 |lpm_counter:519|dffs1
(14) 17 B TFFE t 0 0 0 0 5 0 11 |lpm_counter:519|dffs2
- 18 B TFFE t 0 0 0 0 6 0 5 |lpm_counter:519|dffs3
(13) 19 B DFFE + t 1 0 0 0 5 6 10 |lpm_dff:559|dffs0
- 20 B DFFE + t 2 1 0 0 6 6 10 |lpm_dff:559|dffs1
(12) 21 B DFFE + t 5 4 0 0 7 7 10 |lpm_dff:559|dffs2
(10) 22 B DFFE + t 7 4 1 0 9 8 10 |lpm_dff:559|dffs3
- 103 G DFFE + t 0 0 0 1 0 0 2 :640
- 127 H DFFE + t 0 0 0 1 0 0 2 :641
(73) 112 G DFFE + t 0 0 0 1 0 0 2 :642
(47) 75 E DFFE + t 0 0 0 1 0 0 2 :643
(72) 110 G DFFE + t 0 0 0 1 0 0 2 :644
- 74 E DFFE + t 0 0 0 1 0 0 2 :645
(65) 101 G DFFE + t 0 0 0 1 0 5 0 :646
(98) 8 A DFFE + t 0 0 0 0 1 5 0 :647
(68) 104 G DFFE + t 0 0 0 1 0 0 1 :648
- 66 E DFFE + t 0 0 0 1 0 0 2 :649
- 116 H DFFE + t 0 0 0 1 0 0 2 :650
(56) 88 F DFFE + t 0 0 0 1 0 0 4 :651
- 71 E DFFE + t 0 0 0 0 5 0 4 :652
(62) 96 F DFFE + t 0 0 0 1 0 0 2 :653
- 60 D DFFE + t 0 0 0 1 0 0 2 :654
- 87 F DFFE + t 0 0 0 1 0 0 4 :655
(50) 80 E DFFE + t 0 0 0 0 5 0 4 :656
(52) 81 F DFFE + t 0 0 0 1 0 0 2 :657
(32) 56 D DFFE + t 0 0 0 1 0 0 2 :658
(55) 86 F DFFE + t 0 0 0 1 0 0 4 :659
(49) 78 E DFFE + t 0 0 0 0 5 0 4 :660
- 68 E DFFE + t 0 0 0 1 0 0 4 :661
(48) 77 E DFFE + t 0 0 0 0 5 4 10 :662
- 108 G DFFE + t 4 3 1 0 14 1 0 :663
(31) 57 D DFFE + t 0 0 0 0 1 1 10 :664
- 79 E DFFE + t 0 0 0 1 0 0 1 :665
(67) 102 G DFFE + t 4 3 1 0 14 1 0 :666
- 100 G DFFE + t 4 3 1 0 14 1 0 :667
- 98 G DFFE + t 4 3 1 0 14 1 0 :668
(33) 54 D DFFE + t 0 0 0 0 1 3 10 :669
(42) 69 E DFFE + t 0 0 0 1 0 0 1 :670
- 111 G DFFE + t 4 3 1 0 14 1 0 :671
(71) 109 G DFFE + t 4 3 1 0 14 1 0 :672
(70) 107 G DFFE + t 4 3 1 0 14 1 0 :673
(37) 49 D DFFE + t 0 0 0 0 1 4 10 :674
- 76 E DFFE + t 0 0 0 1 0 0 1 :675
- 106 G DFFE + t 4 3 1 0 14 1 0 :676
(69) 105 G DFFE + t 4 3 1 0 14 1 0 :677
(63) 97 G DFFE + t 4 3 1 0 14 1 0 :678
- 39 C SOFT t 2 2 0 0 4 0 2 :707
(22) 38 C SOFT t 4 2 1 0 6 0 2 :717
(23) 37 C SOFT t 4 1 0 0 8 0 1 :727
- 36 C SOFT t 0 0 0 0 2 0 3 :742
(21) 40 C SOFT t 3 2 0 0 6 0 2 :752
- 42 C SOFT t 4 2 0 0 8 0 1 :762
- 55 D SOFT t 2 2 0 0 4 0 3 :777
(27) 64 D SOFT t 4 2 1 0 6 0 2 :787
(28) 62 D SOFT t 4 1 0 0 8 0 1 :797
- 114 H SOFT t 0 0 0 0 2 0 3 :799
- 124 H SOFT t 0 0 0 0 2 0 3 :801
(9) 24 B SOFT t 2 2 0 0 2 0 3 :804
- 7 A SOFT t 2 1 0 0 4 0 4 :812
(100) 5 A SOFT t 3 2 0 0 6 0 2 :822
- 15 A SOFT t 4 2 0 0 8 0 1 :832
- 31 B SOFT t 2 1 0 0 5 0 2 :847
(7) 27 B SOFT t 5 4 0 0 6 0 2 :857
- 26 B SOFT t 6 4 0 0 8 0 1 :867
- 23 B SOFT t 0 0 0 0 2 0 3 :882
(1) 3 A SOFT t 3 2 0 0 6 0 2 :892
- 2 A SOFT t 4 2 0 0 8 0 1 :902
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
h = Register powers up high
Device-Specific Information: d:\dspexperiment\eda\sellmachine.rpt
sellmachine
** I/O STANDARDS **
Dedicated Pins in Pins in
I/O Standard Input Ref Input Pins I/O Bank 1 I/O Bank 2 Total
LVTTL - 2 8 16 26
Total VCCIO Current is 68 ma (Limit is 1200 ma)
Total GNDIO Current is 68 ma (Limit is 1200 ma)
IOVCC VCCIO VCCIO Current
Group I/O Pins Voltage Current Limit
A: 7/10( 70%) 3.3V 0 ma / 100 ma ( 0%)
B: 0/13( 0%) 3.3V 0 ma / 200 ma ( 0%)
C: 0/14( 0%) 3.3V 0 ma / 200 ma ( 0%)
D: 1/ 3( 33%) 3.3V 4 ma / 100 ma ( 4%)
E: 5/10( 50%) 3.3V 20 ma / 100 ma ( 20%)
F: 1/13( 7%) 3.3V 4 ma / 200 ma ( 2%)
G: 7/14( 50%) 3.3V 28 ma / 200 ma ( 14%)
H: 3/ 3(100%) 3.3V 12 ma / 100 ma ( 12%)
IOGND GNDIO Current
Group I/O Pins Current Limit
A: 10/13( 76%) 40 ma / 200 ma ( 20%)
B: 7/14( 50%) 0 ma / 200 ma ( 0%)
C: 0/13( 0%) 0 ma / 200 ma ( 0%)
D: 3/13( 23%) 12 ma / 200 ma ( 6%)
E: 3/14( 21%) 12 ma / 200 ma ( 6%)
F: 1/13( 7%) 4 ma / 200 ma ( 2%)
Dedicated Inputs:
Pin Type Code VCCIO I/O Standard Input Ref Current Name
90 INPUT - LVTTL - - CLK1K
87 INPUT - LVTTL - - CANCEL
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