📄 sellmachine.rpt
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Project Information d:\dspexperiment\eda\sellmachine.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/02/2004 11:26:11
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
sellmachine
EPM7128BTC100-4 9 17 0 121 85 94 %
User Pins: 9 17 0
Project Information d:\dspexperiment\eda\sellmachine.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'TEST7' is stuck at GND
Warning: Primitive 'TEST6' is stuck at GND
Warning: Primitive 'TEST5' is stuck at GND
Project Information d:\dspexperiment\eda\sellmachine.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK1K' chosen for auto global Clock
INFO: Signal 'CANCEL' chosen for auto global Clock
Project Information d:\dspexperiment\eda\sellmachine.rpt
** FILE HIERARCHY **
|lpm_counter:53|
|lpm_compare:103|
|lpm_compare:103|comptree:comparator|
|lpm_compare:103|comptree:comparator|cmpchain:cmp1|
|lpm_compare:103|comptree:comparator|cmpchain:cmp0|
|lpm_compare:103|comptree:comparator|cmpchain:cmp_end|
|lpm_compare:103|comptree:comparator|comptree:sub_comptree|
|lpm_compare:103|comptree:comparator|comptree:sub_comptree|cmpchain:cmp_end|
|lpm_compare:103|altshift:aeb_ext_lat_ffs|
|lpm_compare:103|altshift:agb_ext_lat_ffs|
|lpm_counter:133|
|lpm_counter:169|
|lpm_counter:205|
|lpm_counter:241|
|lpm_counter:283|
|lpm_compare:319|
|lpm_compare:319|comptree:comparator|
|lpm_compare:319|comptree:comparator|cmpchain:cmp_end|
|lpm_compare:319|altshift:aeb_ext_lat_ffs|
|lpm_compare:319|altshift:agb_ext_lat_ffs|
|lpm_counter:335|
|lpm_counter:375|
|lpm_compare:411|
|lpm_compare:411|comptree:comparator|
|lpm_compare:411|comptree:comparator|cmpchain:cmp_end|
|lpm_compare:411|altshift:aeb_ext_lat_ffs|
|lpm_compare:411|altshift:agb_ext_lat_ffs|
|lpm_counter:427|
|lpm_counter:467|
|lpm_compare:503|
|lpm_compare:503|comptree:comparator|
|lpm_compare:503|comptree:comparator|cmpchain:cmp_end|
|lpm_compare:503|altshift:aeb_ext_lat_ffs|
|lpm_compare:503|altshift:agb_ext_lat_ffs|
|lpm_counter:519|
|lpm_dff:559|
Device-Specific Information: d:\dspexperiment\eda\sellmachine.rpt
sellmachine
***** Logic for device 'sellmachine' compiled without errors.
Device: EPM7128BTC100-4
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
Device-Specific Information: d:\dspexperiment\eda\sellmachine.rpt
sellmachine
** ERROR SUMMARY **
Info: Chip 'sellmachine' in device 'EPM7128BTC100-4' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R
E
J
E R
V C V C E
C C C C C A T T T C L T L J O O
O O O G G G C L N E E E C A C A E U U
I I I G N N N I K G G C G S S S I M O M C T T
N A A N N N D D D N 1 N N E N T T T O P I P T A A
5 4 8 2 1 D * * * T K D D L D 6 5 7 2 3 N 2 A 8 4
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
A1 | 1 75 | OUTA1
START | 2 74 | GND
VCCIO1 | 3 73 | #TDO
#TDI | 4 72 | GND*
GND* | 5 71 | GND*
GND* | 6 70 | GND*
GND* | 7 69 | GND*
GND* | 8 68 | GND*
GND* | 9 67 | GND*
GND* | 10 66 | VCCIO2
GND | 11 65 | GND*
GND* | 12 64 | LAMP1
GND* | 13 EPM7128BTC100-4 63 | GND*
GND* | 14 62 | #TCK
#TMS | 15 61 | GND*
GND* | 16 60 | GND*
GND* | 17 59 | GND
VCCIO1 | 18 58 | GND*
GND* | 19 57 | GND*
GND* | 20 56 | GND*
GND* | 21 55 | GND*
GND* | 22 54 | GND*
GND* | 23 53 | GND*
GND* | 24 52 | GND*
GND* | 25 51 | VCCIO2
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
G G G G G G G G V L G G G V T T G G T T T G G G G
N N N N N N N N C A N N N C E E N N E E E N N N N
D D D D D D D D C M D D D C S S D D S S S D D D D
* * * * * * * I P * * I T T * T T T * * * *
O 0 N 2 3 0 1 4
1 T
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO1 = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO2 = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GND* = These I/O pins can either be left unconnected or connected to GND. Connecting these pins to GND will improve the device's immunity to noise.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\dspexperiment\eda\sellmachine.rpt
sellmachine
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 15/16( 93%) 7/10( 70%) 14/16( 87%) 25/36( 69%)
B: LC17 - LC32 14/16( 87%) 1/10( 10%) 16/16(100%) 21/36( 58%)
C: LC33 - LC48 14/16( 87%) 1/10( 10%) 12/16( 75%) 17/36( 47%)
D: LC49 - LC64 15/16( 93%) 1/10( 10%) 13/16( 81%) 32/36( 88%)
E: LC65 - LC80 16/16(100%) 5/10( 50%) 16/16(100%) 17/36( 47%)
F: LC81 - LC96 16/16(100%) 1/10( 10%) 0/16( 0%) 10/36( 27%)
G: LC97 - LC112 16/16(100%) 2/10( 20%) 16/16(100%) 15/36( 41%)
H: LC113 - LC128 15/16( 93%) 10/10(100%) 16/16(100%) 29/36( 80%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 28/80 ( 35%)
Total logic cells used: 121/128 ( 94%)
Total shareable expanders used: 85/128 ( 66%)
Total Turbo logic cells used: 121/128 ( 94%)
Total shareable expanders not available (n/a): 18/128 ( 14%)
Average fan-in: 6.28
Total fan-in: 761
Total input pins required: 9
Total output pins required: 17
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 121
Total flipflops required: 88
Total product terms required: 387
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 82
Synthesized logic cells: 0/ 128 ( 0%)
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