📄 sellmachinebak.rpt
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^ = Increased input delay
h = Register powers up high
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\dspexperiment\eda\sellmachinebak.rpt
sellmachinebak
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
85 128 H OUTPUT t 4 3 1 0 16 0 0 LAMP0
79 120 H OUTPUT t 4 3 1 0 16 0 0 LAMP1
83 125 H OUTPUT t 4 3 1 0 16 0 0 LAMP2
84 126 H OUTPUT t 2 2 0 0 12 0 0 LAMP3
81 123 H OUTPUT t 1 1 0 0 8 0 0 OUTA1
80 121 H OUTPUT t 0 0 0 0 5 0 0 OUTA4
78 118 H OUTPUT t 0 0 0 0 4 0 0 OUTA8
65 101 G OUTPUT t 0 0 0 0 6 0 0 REJECTA
63 97 G FF + t ! h 0 0 0 0 5 11 0 REJECTCOIN
77 117 H OUTPUT t 2 2 0 0 5 0 0 TEST0
64 99 G OUTPUT t 0 0 0 0 2 0 0 TEST1
76 115 H OUTPUT t 0 0 0 0 2 0 0 TEST2
75 113 H OUTPUT t 0 0 0 0 2 0 0 TEST3
40 65 E FF t 0 0 0 1 2 3 18 TEST4
41 67 E FF t 0 0 0 1 3 2 4 TEST5
44 70 E FF t 0 0 0 1 4 1 2 TEST6
45 72 E FF t 0 0 0 1 5 0 1 TEST7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
h = Register powers up high
Device-Specific Information: d:\dspexperiment\eda\sellmachinebak.rpt
sellmachinebak
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(20) 41 C TFFE t 0 0 0 0 3 0 5 CLK1S
(53) 83 F DFFE + t 0 0 0 0 1 0 1 |lpm_compare:102|comptree:comparator|cmpchain:cmp_end|aeb_out
(57) 89 F DFFE + t 0 0 0 0 4 0 1 |lpm_compare:102|comptree:comparator|cmpchain:cmp0|aeb_out
(61) 94 F DFFE + t 0 0 0 0 4 0 1 |lpm_compare:102|comptree:comparator|cmpchain:cmp1|aeb_out
(28) 62 D DFFE + t 0 0 0 0 2 4 0 |lpm_compare:318|comptree:comparator|cmpchain:cmp_end|aeb_out
- 34 C DFFE + t 0 0 0 0 2 0 4 |lpm_compare:410|comptree:comparator|cmpchain:cmp_end|aeb_out
- 42 C DFFE + t 0 0 0 0 2 0 4 |lpm_compare:502|comptree:comparator|cmpchain:cmp_end|aeb_out
(62) 96 F TFFE + t 0 0 0 0 9 0 10 |lpm_counter:52|dffs0
- 95 F TFFE + t 0 0 0 0 1 0 9 |lpm_counter:52|dffs1
(60) 93 F TFFE + t 0 0 0 0 2 0 8 |lpm_counter:52|dffs2
(56) 88 F TFFE + t 0 0 0 0 9 0 8 |lpm_counter:52|dffs3
(52) 81 F TFFE + t 0 0 0 0 4 0 7 |lpm_counter:52|dffs4
- 84 F TFFE + t 0 0 0 0 5 0 6 |lpm_counter:52|dffs5
(54) 85 F TFFE + t 0 0 0 0 6 0 5 |lpm_counter:52|dffs6
(55) 86 F TFFE + t 0 0 0 0 7 0 4 |lpm_counter:52|dffs7
- 87 F TFFE + t 0 0 0 0 8 0 3 |lpm_counter:52|dffs8
- 114 H TFFE + t 3 3 0 1 7 6 11 |lpm_counter:132|dffs0
(70) 107 G TFFE + t 3 3 0 1 7 6 11 |lpm_counter:132|dffs1
- 122 H TFFE + t 3 3 0 1 7 6 11 |lpm_counter:168|dffs0
- 116 H TFFE + t 3 3 0 1 7 6 11 |lpm_counter:168|dffs1
- 124 H TFFE + t 3 3 0 1 7 5 11 |lpm_counter:204|dffs0
- 127 H TFFE + t 3 3 0 1 7 5 11 |lpm_counter:204|dffs1
(71) 109 G DFFE t 7 3 1 1 12 1 8 |lpm_counter:240|dffs0
(72) 110 G TFFE t 1 0 1 1 8 1 7 |lpm_counter:240|dffs1
- 111 G TFFE t 1 0 1 1 9 1 6 |lpm_counter:240|dffs2
- 103 G TFFE t 1 0 1 1 10 1 5 |lpm_counter:240|dffs3
(68) 104 G TFFE t 1 0 1 1 11 1 4 |lpm_counter:240|dffs4
- 63 D DFFE + t 1 1 0 1 3 0 3 |lpm_counter:282|dffs0
(27) 64 D TFFE + t 1 1 0 1 3 0 3 |lpm_counter:282|dffs1
(21) 40 C DFFE + t 1 1 0 1 3 0 3 |lpm_counter:374|dffs0
(17) 45 C TFFE + t 1 1 0 1 3 0 3 |lpm_counter:374|dffs1
(48) 77 E TFFE t 0 0 0 1 2 0 9 |lpm_counter:426|dffs0
- 76 E TFFE t 0 0 0 1 3 0 7 |lpm_counter:426|dffs1
(49) 78 E TFFE t 0 0 0 1 4 0 5 |lpm_counter:426|dffs2
(47) 75 E TFFE t 0 0 0 1 5 0 2 |lpm_counter:426|dffs3
- 47 C DFFE + t 1 1 0 1 3 0 3 |lpm_counter:466|dffs0
(19) 43 C TFFE + t 1 1 0 1 3 0 3 |lpm_counter:466|dffs1
- 50 D TFFE t 0 0 0 1 2 5 23 |lpm_counter:518|dffs0
(36) 51 D TFFE t 0 0 0 1 3 0 16 |lpm_counter:518|dffs1
- 52 D TFFE t 0 0 0 1 4 0 11 |lpm_counter:518|dffs2
(33) 54 D TFFE t 0 0 0 1 5 0 5 |lpm_counter:518|dffs3
- 82 F DFFE + t 0 0 0 1 0 0 2 :613
- 90 F DFFE + t 0 0 0 1 0 0 2 :614
(58) 91 F DFFE + t 0 0 0 1 0 0 2 :615
- 92 F DFFE + t 0 0 0 1 0 0 2 :616
- 106 G DFFE + t 0 0 0 0 5 4 0 :617
- 44 C DFFE + t 0 0 0 1 0 0 2 :618
- 108 G DFFE + t 0 0 0 0 5 0 4 :619
(35) 53 D DFFE + t 0 0 0 1 0 0 2 :620
- 100 G DFFE + t 0 0 0 0 5 0 4 :621
(50) 80 E SOFT t 2 2 0 0 4 0 2 :652
- 79 E SOFT t 4 2 1 0 6 0 2 :662
- 74 E SOFT t 4 1 0 0 8 0 1 :672
(42) 69 E SOFT t 0 0 0 0 2 0 3 :687
- 71 E SOFT t 3 2 0 0 6 0 2 :697
- 68 E SOFT t 4 2 0 0 8 0 1 :707
- 66 E SOFT t 2 2 0 0 4 0 3 :722
(46) 73 E SOFT t 4 2 1 0 6 0 2 :732
(24) 35 C SOFT t 4 1 0 0 8 0 1 :742
(69) 105 G SOFT t 0 0 0 0 2 5 4 :744
(67) 102 G SOFT t 0 0 0 0 2 5 4 :746
- 98 G SOFT t 2 2 0 0 2 5 3 :749
(73) 112 G SOFT t 2 1 0 0 4 0 4 :757
(16) 46 C SOFT t 3 2 0 0 6 0 2 :767
(25) 33 C SOFT t 4 2 0 0 8 0 1 :777
- 55 D SOFT t 2 1 0 0 5 0 2 :792
(32) 56 D SOFT t 5 4 0 0 6 0 2 :802
- 58 D SOFT t 6 4 0 0 8 0 1 :812
(30) 59 D SOFT t 0 0 0 0 2 0 3 :827
(23) 37 C SOFT t 3 2 0 0 6 0 2 :837
(22) 38 C SOFT t 4 2 0 0 8 0 1 :847
- 60 D SOFT t 0 0 0 0 3 4 0 :849
- 119 H SOFT t 0 0 0 0 2 4 0 :851
(37) 49 D SOFT t 2 2 0 0 5 6 0 :862
(29) 61 D SOFT t 6 5 1 0 8 7 0 :872
(31) 57 D SOFT t 6 3 0 0 8 8 0 :882
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
h = Register powers up high
Device-Specific Information: d:\dspexperiment\eda\sellmachinebak.rpt
sellmachinebak
** I/O STANDARDS **
Dedicated Pins in Pins in
I/O Standard Input Ref Input Pins I/O Bank 1 I/O Bank 2 Total
LVTTL - 1 7 17 25
Total VCCIO Current is 68 ma (Limit is 1200 ma)
Total GNDIO Current is 68 ma (Limit is 1200 ma)
IOVCC VCCIO VCCIO Current
Group I/O Pins Voltage Current Limit
A: 7/10( 70%) 3.3V 0 ma / 100 ma ( 0%)
B: 0/13( 0%) 3.3V 0 ma / 200 ma ( 0%)
C: 0/14( 0%) 3.3V 0 ma / 200 ma ( 0%)
D: 0/ 3( 0%) 3.3V 0 ma / 100 ma ( 0%)
E: 4/10( 40%) 3.3V 16 ma / 100 ma ( 16%)
F: 3/13( 23%) 3.3V 12 ma / 200 ma ( 6%)
G: 7/14( 50%) 3.3V 28 ma / 200 ma ( 14%)
H: 3/ 3(100%) 3.3V 12 ma / 100 ma ( 12%)
IOGND GNDIO Current
Group I/O Pins Current Limit
A: 10/13( 76%) 40 ma / 200 ma ( 20%)
B: 7/14( 50%) 0 ma / 200 ma ( 0%)
C: 0/13( 0%) 0 ma / 200 ma ( 0%)
D: 2/13( 15%) 8 ma / 200 ma ( 4%)
E: 2/14( 14%) 8 ma / 200 ma ( 4%)
F: 3/13( 23%) 12 ma / 200 ma ( 6%)
Dedicated Inputs:
Pin Type Code VCCIO I/O Standard Input Ref Current Name
87 INPUT - LVTTL - - CLK1K
IOVCC group A: VCCIO Current is 0 ma (Limit is 100 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
96 INPUT - LVTTL - - COIN2
97 INPUT - LVTTL - - A8
98 INPUT - LVTTL - - A4
99 INPUT - LVTTL - - COIN1
100 INPUT - LVTTL - - COIN5
1 INPUT - LVTTL - - A1
2 INPUT - LVTTL - - START
IOVCC group E: VCCIO Current is 16 ma (Limit is 100 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
40 OUTPUT 3.3V LVTTL - 4 ma TEST4
41 OUTPUT 3.3V LVTTL - 4 ma TEST5
44 OUTPUT 3.3V LVTTL - 4 ma TEST6
45 OUTPUT 3.3V LVTTL - 4 ma TEST7
IOVCC group F: VCCIO Current is 12 ma (Limit is 200 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
63 OUTPUT 3.3V LVTTL - 4 ma REJECTCOIN
64 OUTPUT 3.3V LVTTL - 4 ma TEST1
65 OUTPUT 3.3V LVTTL - 4 ma REJECTA
IOVCC group G: VCCIO Current is 28 ma (Limit is 200 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
75 OUTPUT 3.3V LVTTL - 4 ma TEST3
76 OUTPUT 3.3V LVTTL - 4 ma TEST2
77 OUTPUT 3.3V LVTTL - 4 ma TEST0
78 OUTPUT 3.3V LVTTL - 4 ma OUTA8
79 OUTPUT 3.3V LVTTL - 4 ma LAMP1
80 OUTPUT 3.3V LVTTL - 4 ma OUTA4
81 OUTPUT 3.3V LVTTL - 4 ma OUTA1
IOVCC group H: VCCIO Current is 12 ma (Limit is 100 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
83 OUTPUT 3.3V LVTTL - 4 ma LAMP2
84 OUTPUT 3.3V LVTTL - 4 ma LAMP3
85 OUTPUT 3.3V LVTTL - 4 ma LAMP0
IOGND group A: GNDIO Current is 40 ma (Limit is 200 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
75 OUTPUT - LVTTL - 4 ma TEST3
76 OUTPUT - LVTTL - 4 ma TEST2
77 OUTPUT - LVTTL - 4 ma TEST0
78 OUTPUT - LVTTL - 4 ma OUTA8
79 OUTPUT - LVTTL - 4 ma LAMP1
80 OUTPUT - LVTTL - 4 ma OUTA4
81 OUTPUT - LVTTL - 4 ma OUTA1
83 OUTPUT - LVTTL - 4 ma LAMP2
84 OUTPUT - LVTTL - 4 ma LAMP3
85 OUTPUT - LVTTL - 4 ma LAMP0
IOGND group B: GNDIO Current is 0 ma (Limit is 200 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
96 INPUT - LVTTL - - COIN2
97 INPUT - LVTTL - - A8
98 INPUT - LVTTL - - A4
99 INPUT - LVTTL - - COIN1
100 INPUT - LVTTL - - COIN5
1 INPUT - LVTTL - - A1
2 INPUT - LVTTL - - START
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