q7230.tan.rpt

PLD-N分频程序

; N/A           ; None        ; -17.500 ns ; OE     ; count[7] ; CLK      ;
; N/A           ; None        ; -17.500 ns ; OE     ; count[6] ; CLK      ;
; N/A           ; None        ; -17.500 ns ; Din[0] ; count[4] ; CLK      ;
; N/A           ; None        ; -17.500 ns ; Din[0] ; count[2] ; CLK      ;
; N/A           ; None        ; -17.500 ns ; Din[0] ; count[5] ; CLK      ;
; N/A           ; None        ; -17.500 ns ; Din[0] ; count[3] ; CLK      ;
; N/A           ; None        ; -17.500 ns ; Din[0] ; count[7] ; CLK      ;
; N/A           ; None        ; -17.500 ns ; Din[0] ; count[6] ; CLK      ;
; N/A           ; None        ; -17.600 ns ; reset  ; count[4] ; CLK      ;
; N/A           ; None        ; -17.600 ns ; reset  ; count[2] ; CLK      ;
; N/A           ; None        ; -17.600 ns ; reset  ; count[5] ; CLK      ;
; N/A           ; None        ; -17.600 ns ; reset  ; count[3] ; CLK      ;
; N/A           ; None        ; -17.600 ns ; reset  ; count[7] ; CLK      ;
; N/A           ; None        ; -17.600 ns ; reset  ; count[6] ; CLK      ;
; N/A           ; None        ; -18.500 ns ; Din[6] ; count[4] ; CLK      ;
; N/A           ; None        ; -18.500 ns ; Din[6] ; count[2] ; CLK      ;
; N/A           ; None        ; -18.500 ns ; Din[6] ; count[5] ; CLK      ;
; N/A           ; None        ; -18.500 ns ; Din[6] ; count[3] ; CLK      ;
; N/A           ; None        ; -18.500 ns ; Din[6] ; count[7] ; CLK      ;
; N/A           ; None        ; -18.500 ns ; Din[6] ; count[6] ; CLK      ;
+---------------+-------------+------------+--------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition
    Info: Processing started: Wed Jan 04 09:38:54 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Q7230 -c Q7230
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 1 nodes
    Info: Node "Q[7]~239"
Info: Found combinational loop of 1 nodes
    Info: Node "Q[6]~235"
Info: Found combinational loop of 1 nodes
    Info: Node "Q[4]~219"
Info: Found combinational loop of 1 nodes
    Info: Node "Q[2]~223"
Info: Found combinational loop of 1 nodes
    Info: Node "Q[1]~215"
Info: Found combinational loop of 1 nodes
    Info: Node "Q[0]~211"
Info: Found combinational loop of 1 nodes
    Info: Node "Q[5]~231"
Info: Found combinational loop of 1 nodes
    Info: Node "Q[3]~227"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
    Info: Assuming node "NAB" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "CK~20" as buffer
    Info: Detected ripple clock "CP_Q" as buffer
Info: Clock "CLK" has Internal fmax of 39.22 MHz between source register "count[4]" and destination register "count[6]" (period= 25.5 ns)
    Info: + Longest register to register delay is 21.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 15; REG Node = 'count[4]'
        Info: 2: + IC(2.200 ns) + CELL(4.000 ns) = 6.200 ns; Loc. = SEXP25; Fanout = 2; COMB Node = 'reduce_nor~16'
        Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 7.400 ns; Loc. = LC20; Fanout = 1; COMB Node = 'reduce_nor~42'
        Info: 4: + IC(0.000 ns) + CELL(4.400 ns) = 11.800 ns; Loc. = LC21; Fanout = 7; COMB Node = 'reduce_nor~25'
        Info: 5: + IC(2.100 ns) + CELL(4.000 ns) = 17.900 ns; Loc. = SEXP1; Fanout = 12; COMB Node = 'rtl~560'
        Info: 6: + IC(0.000 ns) + CELL(3.300 ns) = 21.200 ns; Loc. = LC15; Fanout = 8; REG Node = 'count[6]'
        Info: Total cell delay = 16.900 ns ( 79.72 % )
        Info: Total interconnect delay = 4.300 ns ( 20.28 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC15; Fanout = 8; REG Node = 'count[6]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC5; Fanout = 15; REG Node = 'count[4]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.500 ns
    Info: + Micro setup delay of destination is 2.800 ns
Info: No valid register-to-register data paths exist for clock "NAB"
Info: tsu for register "count[4]" (data pin = "reset", clock pin = "CLK") is 32.800 ns
    Info: + Longest pin to register delay is 33.400 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_11; Fanout = 42; PIN Node = 'reset'
        Info: 2: + IC(2.200 ns) + CELL(4.000 ns) = 7.700 ns; Loc. = SEXP28; Fanout = 16; COMB Node = 'Q[0]$en_or~41sexp'
        Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 12.300 ns; Loc. = LC29; Fanout = 9; COMB LOOP Node = 'Q[0]~211'
            Info: Loc. = LC29; Node "Q[0]~211"
        Info: 4: + IC(2.100 ns) + CELL(4.000 ns) = 18.400 ns; Loc. = SEXP22; Fanout = 2; COMB Node = 'reduce_nor~17'
        Info: 5: + IC(0.000 ns) + CELL(1.200 ns) = 19.600 ns; Loc. = LC20; Fanout = 1; COMB Node = 'reduce_nor~42'
        Info: 6: + IC(0.000 ns) + CELL(4.400 ns) = 24.000 ns; Loc. = LC21; Fanout = 7; COMB Node = 'reduce_nor~25'
        Info: 7: + IC(2.100 ns) + CELL(4.000 ns) = 30.100 ns; Loc. = SEXP1; Fanout = 12; COMB Node = 'rtl~560'
        Info: 8: + IC(0.000 ns) + CELL(3.300 ns) = 33.400 ns; Loc. = LC5; Fanout = 15; REG Node = 'count[4]'
        Info: Total cell delay = 27.000 ns ( 80.84 % )
        Info: Total interconnect delay = 6.400 ns ( 19.16 % )
    Info: + Micro setup delay of destination is 2.800 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC5; Fanout = 15; REG Node = 'count[4]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
Info: tco from clock "CLK" to destination pin "NDQ" through register "D_Q" is 23.500 ns
    Info: + Longest clock path from clock "CLK" to source register is 13.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(2.800 ns) = 4.900 ns; Loc. = LC11; Fanout = 4; REG Node = 'CP_Q'
        Info: 3: + IC(2.100 ns) + CELL(4.000 ns) = 11.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = 'CK~20'
        Info: 4: + IC(0.000 ns) + CELL(2.500 ns) = 13.500 ns; Loc. = LC8; Fanout = 2; REG Node = 'D_Q'
        Info: Total cell delay = 11.400 ns ( 84.44 % )
        Info: Total interconnect delay = 2.100 ns ( 15.56 % )
    Info: + Micro clock to output delay of source is 1.500 ns
    Info: + Longest register to pin delay is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 2; REG Node = 'D_Q'
        Info: 2: + IC(2.100 ns) + CELL(4.600 ns) = 6.700 ns; Loc. = LC17; Fanout = 1; COMB Node = 'D_Q~6'
        Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 8.500 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'NDQ'
        Info: Total cell delay = 6.400 ns ( 75.29 % )
        Info: Total interconnect delay = 2.100 ns ( 24.71 % )
Info: Longest tpd from source pin "NAB" to destination pin "CK" is 10.000 ns
    Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_34; Fanout = 2; CLK Node = 'NAB'
    Info: 2: + IC(2.100 ns) + CELL(4.600 ns) = 8.200 ns; Loc. = LC3; Fanout = 1; COMB Node = 'CK~18'
    Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 10.000 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'CK'
    Info: Total cell delay = 7.900 ns ( 79.00 % )
    Info: Total interconnect delay = 2.100 ns ( 21.00 % )
Info: th for register "D_Q" (data pin = "D", clock pin = "CLK") is 7.900 ns
    Info: + Longest clock path from clock "CLK" to destination register is 13.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(2.800 ns) = 4.900 ns; Loc. = LC11; Fanout = 4; REG Node = 'CP_Q'
        Info: 3: + IC(2.100 ns) + CELL(4.000 ns) = 11.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = 'CK~20'
        Info: 4: + IC(0.000 ns) + CELL(2.500 ns) = 13.500 ns; Loc. = LC8; Fanout = 2; REG Node = 'D_Q'
        Info: Total cell delay = 11.400 ns ( 84.44 % )
        Info: Total interconnect delay = 2.100 ns ( 15.56 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_21; Fanout = 1; PIN Node = 'D'
        Info: 2: + IC(2.100 ns) + CELL(3.300 ns) = 6.900 ns; Loc. = LC8; Fanout = 2; REG Node = 'D_Q'
        Info: Total cell delay = 4.800 ns ( 69.57 % )
        Info: Total interconnect delay = 2.100 ns ( 30.43 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Jan 04 09:38:56 2006
    Info: Elapsed time: 00:00:03