q7230.map.qmsg

PLD-N分频程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 156 11/29/2004 SJ Web Edition " "Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 04 09:38:15 2006 " "Info: Processing started: Wed Jan 04 09:38:15 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Q7230 -c Q7230 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Q7230 -c Q7230" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TOP.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TOP.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TOP-a " "Info: Found design unit 1: TOP-a" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 19 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 TOP " "Info: Found entity 1: TOP" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "count TOP.vhd(20) " "Warning: VHDL Signal Declaration warning at TOP.vhd(20): ignored default value for signal \"count\"" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "Q TOP.vhd(21) " "Warning: VHDL Signal Declaration warning at TOP.vhd(21): ignored default value for signal \"Q\"" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "CP_Q TOP.vhd(22) " "Warning: VHDL Signal Declaration warning at TOP.vhd(22): ignored default value for signal \"CP_Q\"" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "D_Q TOP.vhd(23) " "Warning: VHDL Signal Declaration warning at TOP.vhd(23): ignored default value for signal \"D_Q\"" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "NAB TOP.vhd(48) " "Warning: VHDL Process Statement warning at TOP.vhd(48): signal \"NAB\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CP_Q TOP.vhd(48) " "Warning: VHDL Process Statement warning at TOP.vhd(48): signal \"CP_Q\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din TOP.vhd(58) " "Warning: VHDL Process Statement warning at TOP.vhd(58): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 58 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Q TOP.vhd(53) " "Warning: VHDL Process Statement warning at TOP.vhd(53): signal or variable \"Q\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"Q\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D_Q TOP.vhd(69) " "Warning: VHDL Process Statement warning at TOP.vhd(69): signal \"D_Q\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 69 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../comsof/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/comsof/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../comsof/altera/quartus42/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/comsof/altera/quartus42/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../comsof/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/comsof/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../comsof/altera/quartus42/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "d:/comsof/altera/quartus42/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../comsof/altera/quartus42/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../comsof/altera/quartus42/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/comsof/altera/quartus42/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "8 " "Info: Ignored 8 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "8 " "Info: Ignored 8 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK " "Info: Promoted clock signal driven by pin \"CLK\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK " "Info: Promoted clock signal driven by pin \"CLK\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "63 " "Info: Implemented 63 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "28 " "Info: Implemented 28 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "16 " "Info: Implemented 16 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 04 09:38:36 2006 " "Info: Processing ended: Wed Jan 04 09:38:36 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Info: Elapsed time: 00:00:22" {  } {  } 0}  } {  } 0}