📄 q7230.tan.qmsg

📁 PLD-N分频程序
💻 QMSG
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{ "Info" "ITAN_NO_REG2REG_EXIST" "NAB " "Info: No valid register-to-register data paths exist for clock \"NAB\"" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "count\[4\] reset CLK 32.800 ns register " "Info: tsu for register \"count\[4\]\" (data pin = \"reset\", clock pin = \"CLK\") is 32.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "33.400 ns + Longest pin register " "Info: + Longest pin to register delay is 33.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns reset 1 PIN PIN_11 42 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_11; Fanout = 42; PIN Node = 'reset'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { reset } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(4.000 ns) 7.700 ns Q\[0\]\$en_or~41sexp 2 COMB SEXP28 16 " "Info: 2: + IC(2.200 ns) + CELL(4.000 ns) = 7.700 ns; Loc. = SEXP28; Fanout = 16; COMB Node = 'Q\[0\]\$en_or~41sexp'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.200 ns" { reset Q[0]$en_or~41sexp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 12.300 ns Q\[0\]~211 3 COMB LOOP LC29 9 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 12.300 ns; Loc. = LC29; Fanout = 9; COMB LOOP Node = 'Q\[0\]~211'" { { "Info" "ITDB_PART_OF_SCC" "Q\[0\]~211 LC29 " "Info: Loc. = LC29; Node \"Q\[0\]~211\"" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { Q[0]~211 } "NODE_NAME" } "" } }  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { Q[0]~211 } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "4.600 ns" { Q[0]$en_or~41sexp Q[0]~211 } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(4.000 ns) 18.400 ns reduce_nor~17 4 COMB SEXP22 2 " "Info: 4: + IC(2.100 ns) + CELL(4.000 ns) = 18.400 ns; Loc. = SEXP22; Fanout = 2; COMB Node = 'reduce_nor~17'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.100 ns" { Q[0]~211 reduce_nor~17 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 19.600 ns reduce_nor~42 5 COMB LC20 1 " "Info: 5: + IC(0.000 ns) + CELL(1.200 ns) = 19.600 ns; Loc. = LC20; Fanout = 1; COMB Node = 'reduce_nor~42'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "1.200 ns" { reduce_nor~17 reduce_nor~42 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 24.000 ns reduce_nor~25 6 COMB LC21 7 " "Info: 6: + IC(0.000 ns) + CELL(4.400 ns) = 24.000 ns; Loc. = LC21; Fanout = 7; COMB Node = 'reduce_nor~25'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "4.400 ns" { reduce_nor~42 reduce_nor~25 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(4.000 ns) 30.100 ns rtl~560 7 COMB SEXP1 12 " "Info: 7: + IC(2.100 ns) + CELL(4.000 ns) = 30.100 ns; Loc. = SEXP1; Fanout = 12; COMB Node = 'rtl~560'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.100 ns" { reduce_nor~25 rtl~560 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.300 ns) 33.400 ns count\[4\] 8 REG LC5 15 " "Info: 8: + IC(0.000 ns) + CELL(3.300 ns) = 33.400 ns; Loc. = LC5; Fanout = 15; REG Node = 'count\[4\]'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.300 ns" { rtl~560 count[4] } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "27.000 ns 80.84 % " "Info: Total cell delay = 27.000 ns ( 80.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.400 ns 19.16 % " "Info: Total interconnect delay = 6.400 ns ( 19.16 % )" {  } {  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "33.400 ns" { reset Q[0]$en_or~41sexp Q[0]~211 reduce_nor~17 reduce_nor~42 reduce_nor~25 rtl~560 count[4] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "33.400 ns" { reset reset~out Q[0]$en_or~41sexp Q[0]~211 reduce_nor~17 reduce_nor~42 reduce_nor~25 rtl~560 count[4] } { 0.000ns 0.000ns 2.200ns 0.000ns 2.100ns 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 1.500ns 4.000ns 4.600ns 4.000ns 1.200ns 4.400ns 4.000ns 3.300ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.800 ns + " "Info: + Micro setup delay of destination is 2.800 ns" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 2.100 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { CLK } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.400 ns count\[4\] 2 REG LC5 15 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC5; Fanout = 15; REG Node = 'count\[4\]'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "1.300 ns" { CLK count[4] } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.400 ns" { CLK count[4] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "3.400 ns" { CLK CLK~out count[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } }  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "33.400 ns" { reset Q[0]$en_or~41sexp Q[0]~211 reduce_nor~17 reduce_nor~42 reduce_nor~25 rtl~560 count[4] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "33.400 ns" { reset reset~out Q[0]$en_or~41sexp Q[0]~211 reduce_nor~17 reduce_nor~42 reduce_nor~25 rtl~560 count[4] } { 0.000ns 0.000ns 2.200ns 0.000ns 2.100ns 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 1.500ns 4.000ns 4.600ns 4.000ns 1.200ns 4.400ns 4.000ns 3.300ns } } } { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.400 ns" { CLK count[4] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "3.400 ns" { CLK CLK~out count[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK NDQ D_Q 23.500 ns register " "Info: tco from clock \"CLK\" to destination pin \"NDQ\" through register \"D_Q\" is 23.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 13.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 13.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 2.100 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { CLK } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 4.900 ns CP_Q 2 REG LC11 4 " "Info: 2: + IC(0.000 ns) + CELL(2.800 ns) = 4.900 ns; Loc. = LC11; Fanout = 4; REG Node = 'CP_Q'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "2.800 ns" { CLK CP_Q } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(4.000 ns) 11.000 ns CK~20 3 COMB SEXP5 1 " "Info: 3: + IC(2.100 ns) + CELL(4.000 ns) = 11.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = 'CK~20'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.100 ns" { CP_Q CK~20 } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.500 ns D_Q 4 REG LC8 2 " "Info: 4: + IC(0.000 ns) + CELL(2.500 ns) = 13.500 ns; Loc. = LC8; Fanout = 2; REG Node = 'D_Q'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "2.500 ns" { CK~20 D_Q } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 66 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.400 ns 84.44 % " "Info: Total cell delay = 11.400 ns ( 84.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 15.56 % " "Info: Total interconnect delay = 2.100 ns ( 15.56 % )" {  } {  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "13.500 ns" { CLK CP_Q CK~20 D_Q } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "13.500 ns" { CLK CLK~out CP_Q CK~20 D_Q } { 0.000ns 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 2.100ns 2.800ns 4.000ns 2.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.500 ns + " "Info: + Micro clock to output delay of source is 1.500 ns" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 66 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns + Longest register pin " "Info: + Longest register to pin delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D_Q 1 REG LC8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 2; REG Node = 'D_Q'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { D_Q } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 66 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(4.600 ns) 6.700 ns D_Q~6 2 COMB LC17 1 " "Info: 2: + IC(2.100 ns) + CELL(4.600 ns) = 6.700 ns; Loc. = LC17; Fanout = 1; COMB Node = 'D_Q~6'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.700 ns" { D_Q D_Q~6 } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 66 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 8.500 ns NDQ 3 PIN PIN_41 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 8.500 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'NDQ'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "1.800 ns" { D_Q~6 NDQ } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.400 ns 75.29 % " "Info: Total cell delay = 6.400 ns ( 75.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 24.71 % " "Info: Total interconnect delay = 2.100 ns ( 24.71 % )" {  } {  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "8.500 ns" { D_Q D_Q~6 NDQ } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { D_Q D_Q~6 NDQ } { 0.000ns 2.100ns 0.000ns } { 0.000ns 4.600ns 1.800ns } } }  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "13.500 ns" { CLK CP_Q CK~20 D_Q } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "13.500 ns" { CLK CLK~out CP_Q CK~20 D_Q } { 0.000ns 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 2.100ns 2.800ns 4.000ns 2.500ns } } } { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "8.500 ns" { D_Q D_Q~6 NDQ } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { D_Q D_Q~6 NDQ } { 0.000ns 2.100ns 0.000ns } { 0.000ns 4.600ns 1.800ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "NAB CK 10.000 ns Longest " "Info: Longest tpd from source pin \"NAB\" to destination pin \"CK\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns NAB 1 CLK PIN_34 2 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_34; Fanout = 2; CLK Node = 'NAB'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { NAB } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(4.600 ns) 8.200 ns CK~18 2 COMB LC3 1 " "Info: 2: + IC(2.100 ns) + CELL(4.600 ns) = 8.200 ns; Loc. = LC3; Fanout = 1; COMB Node = 'CK~18'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.700 ns" { NAB CK~18 } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 10.000 ns CK 3 PIN PIN_6 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 10.000 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'CK'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "1.800 ns" { CK~18 CK } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.900 ns 79.00 % " "Info: Total cell delay = 7.900 ns ( 79.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 21.00 % " "Info: Total interconnect delay = 2.100 ns ( 21.00 % )" {  } {  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "10.000 ns" { NAB CK~18 CK } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { NAB NAB~out CK~18 CK } { 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 1.500ns 4.600ns 1.800ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "D_Q D CLK 7.900 ns register " "Info: th for register \"D_Q\" (data pin = \"D\", clock pin = \"CLK\") is 7.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 13.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 13.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 2.100 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { CLK } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 4.900 ns CP_Q 2 REG LC11 4 " "Info: 2: + IC(0.000 ns) + CELL(2.800 ns) = 4.900 ns; Loc. = LC11; Fanout = 4; REG Node = 'CP_Q'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "2.800 ns" { CLK CP_Q } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(4.000 ns) 11.000 ns CK~20 3 COMB SEXP5 1 " "Info: 3: + IC(2.100 ns) + CELL(4.000 ns) = 11.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = 'CK~20'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.100 ns" { CP_Q CK~20 } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.500 ns D_Q 4 REG LC8 2 " "Info: 4: + IC(0.000 ns) + CELL(2.500 ns) = 13.500 ns; Loc. = LC8; Fanout = 2; REG Node = 'D_Q'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "2.500 ns" { CK~20 D_Q } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 66 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.400 ns 84.44 % " "Info: Total cell delay = 11.400 ns ( 84.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 15.56 % " "Info: Total interconnect delay = 2.100 ns ( 15.56 % )" {  } {  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "13.500 ns" { CLK CP_Q CK~20 D_Q } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "13.500 ns" { CLK CLK~out CP_Q CK~20 D_Q } { 0.000ns 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 2.100ns 2.800ns 4.000ns 2.500ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 66 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns D 1 PIN PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_21; Fanout = 1; PIN Node = 'D'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { D } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(3.300 ns) 6.900 ns D_Q 2 REG LC8 2 " "Info: 2: + IC(2.100 ns) + CELL(3.300 ns) = 6.900 ns; Loc. = LC8; Fanout = 2; REG Node = 'D_Q'" {  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "5.400 ns" { D D_Q } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 66 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.800 ns 69.57 % " "Info: Total cell delay = 4.800 ns ( 69.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 30.43 % " "Info: Total interconnect delay = 2.100 ns ( 30.43 % )" {  } {  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.900 ns" { D D_Q } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "6.900 ns" { D D~out D_Q } { 0.000ns 0.000ns 2.100ns } { 0.000ns 1.500ns 3.300ns } } }  } 0}  } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "13.500 ns" { CLK CP_Q CK~20 D_Q } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "13.500 ns" { CLK CLK~out CP_Q CK~20 D_Q } { 0.000ns 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 2.100ns 2.800ns 4.000ns 2.500ns } } } { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.900 ns" { D D_Q } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "6.900 ns" { D D~out D_Q } { 0.000ns 0.000ns 2.100ns } { 0.000ns 1.500ns 3.300ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 04 09:38:56 2006 " "Info: Processing ended: Wed Jan 04 09:38:56 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}
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