📄 q7230.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Q\[2\]~223 " "Info: Node \"Q\[2\]~223\"" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0} } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Q\[1\]~215 " "Info: Node \"Q\[1\]~215\"" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0} } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Q\[0\]~211 " "Info: Node \"Q\[0\]~211\"" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0} } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Q\[5\]~231 " "Info: Node \"Q\[5\]~231\"" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0} } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Q\[3\]~227 " "Info: Node \"Q\[3\]~227\"" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0} } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 53 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 8 -1 0 } } { "d:/comsof/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/comsof/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "NAB " "Info: Assuming node \"NAB\" is an undefined clock" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 10 -1 0 } } { "d:/comsof/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/comsof/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "NAB" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "CK~20 " "Info: Detected gated clock \"CK~20\" as buffer" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 13 -1 0 } } { "d:/comsof/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/comsof/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CK~20" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "CP_Q " "Info: Detected ripple clock \"CP_Q\" as buffer" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } } { "d:/comsof/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/comsof/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CP_Q" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register count\[4\] register count\[6\] 39.22 MHz 25.5 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 39.22 MHz between source register \"count\[4\]\" and destination register \"count\[6\]\" (period= 25.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.200 ns + Longest register register " "Info: + Longest register to register delay is 21.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[4\] 1 REG LC5 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 15; REG Node = 'count\[4\]'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { count[4] } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(4.000 ns) 6.200 ns reduce_nor~16 2 COMB SEXP25 2 " "Info: 2: + IC(2.200 ns) + CELL(4.000 ns) = 6.200 ns; Loc. = SEXP25; Fanout = 2; COMB Node = 'reduce_nor~16'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.200 ns" { count[4] reduce_nor~16 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 7.400 ns reduce_nor~42 3 COMB LC20 1 " "Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 7.400 ns; Loc. = LC20; Fanout = 1; COMB Node = 'reduce_nor~42'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "1.200 ns" { reduce_nor~16 reduce_nor~42 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 11.800 ns reduce_nor~25 4 COMB LC21 7 " "Info: 4: + IC(0.000 ns) + CELL(4.400 ns) = 11.800 ns; Loc. = LC21; Fanout = 7; COMB Node = 'reduce_nor~25'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "4.400 ns" { reduce_nor~42 reduce_nor~25 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(4.000 ns) 17.900 ns rtl~560 5 COMB SEXP1 12 " "Info: 5: + IC(2.100 ns) + CELL(4.000 ns) = 17.900 ns; Loc. = SEXP1; Fanout = 12; COMB Node = 'rtl~560'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "6.100 ns" { reduce_nor~25 rtl~560 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.300 ns) 21.200 ns count\[6\] 6 REG LC15 8 " "Info: 6: + IC(0.000 ns) + CELL(3.300 ns) = 21.200 ns; Loc. = LC15; Fanout = 8; REG Node = 'count\[6\]'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.300 ns" { rtl~560 count[6] } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.900 ns 79.72 % " "Info: Total cell delay = 16.900 ns ( 79.72 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns 20.28 % " "Info: Total interconnect delay = 4.300 ns ( 20.28 % )" { } { } 0} } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "21.200 ns" { count[4] reduce_nor~16 reduce_nor~42 reduce_nor~25 rtl~560 count[6] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "21.200 ns" { count[4] reduce_nor~16 reduce_nor~42 reduce_nor~25 rtl~560 count[6] } { 0.000ns 2.200ns 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 4.000ns 1.200ns 4.400ns 4.000ns 3.300ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 2.100 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { CLK } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.400 ns count\[6\] 2 REG LC15 8 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC15; Fanout = 8; REG Node = 'count\[6\]'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "1.300 ns" { CLK count[6] } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.400 ns" { CLK count[6] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "3.400 ns" { CLK CLK~out count[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 2.100 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "" { CLK } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.400 ns count\[4\] 2 REG LC5 15 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC5; Fanout = 15; REG Node = 'count\[4\]'" { } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "1.300 ns" { CLK count[4] } "NODE_NAME" } "" } } { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.400 ns" { CLK count[4] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "3.400 ns" { CLK CLK~out count[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } } } 0} } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.400 ns" { CLK count[6] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "3.400 ns" { CLK CLK~out count[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } } { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.400 ns" { CLK count[4] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "3.400 ns" { CLK CLK~out count[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.500 ns + " "Info: + Micro clock to output delay of source is 1.500 ns" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.800 ns + " "Info: + Micro setup delay of destination is 2.800 ns" { } { { "TOP.vhd" "" { Text "D:/PLD-Test/NEW/Q7230/TOP.vhd" 29 -1 0 } } } 0} } { { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "21.200 ns" { count[4] reduce_nor~16 reduce_nor~42 reduce_nor~25 rtl~560 count[6] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "21.200 ns" { count[4] reduce_nor~16 reduce_nor~42 reduce_nor~25 rtl~560 count[6] } { 0.000ns 2.200ns 0.000ns 0.000ns 2.100ns 0.000ns } { 0.000ns 4.000ns 1.200ns 4.400ns 4.000ns 3.300ns } } } { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.400 ns" { CLK count[6] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "3.400 ns" { CLK CLK~out count[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } } { "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" "" { Report "D:/PLD-Test/NEW/Q7230/db/Q7230_cmp.qrpt" Compiler "Q7230" "UNKNOWN" "V1" "D:/PLD-Test/NEW/Q7230/db/Q7230.quartus_db" { Floorplan "D:/PLD-Test/NEW/Q7230/" "" "3.400 ns" { CLK count[4] } "NODE_NAME" } "" } } { "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/comsof/altera/quartus42/bin/Technology_Viewer.qrui" "3.400 ns" { CLK CLK~out count[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } } } 0}
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