q7230.map.talkback.xml

PLD-N分频程序

<!--
This XML file (created on Wed Jan 04 09:38:37 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>4.2</ver>
<schema>quartus_version_4.2_build_156.xsd</schema><license>
	<host_id>000d567730b7</host_id>
	<nic_id>000d567730b7</nic_id>
	<cdrive_id>741bc671</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>4.2</version>
	<build>Build 156</build>
	<module>quartus_map.exe</module>
	<edition>Web Edition</edition>
	<compilation_end_time>Wed Jan 04 09:38:37 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows 2000</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2404</cpu_freq>
	</cpu>
	<ram units="MB">239</ram>
</machine>
<top_file>D:/PLD-Test/NEW/Q7230/Q7230</top_file>
<mep_data>
	<command_line>quartus_map --import_settings_files=on --export_settings_files=off Q7230 -c Q7230</command_line>
</mep_data>
<software_data>
	<speed_disk_usage_tradeoff>normal</speed_disk_usage_tradeoff>
</software_data>
<analysis___synthesis_settings>
	<row>
		<option>Device</option>
		<setting>EPM3032ALC44-10</setting>
	</row>
	<row>
		<option>Family name</option>
		<setting>MAX3000A</setting>
		<default_value>Stratix</default_value>
	</row>
	<row>
		<option>Top-level entity name</option>
		<setting>TOP</setting>
		<default_value>Q7230</default_value>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Create Debugging Nodes for IP Cores</option>
		<setting>off</setting>
		<default_value>off</default_value>
	</row>
	<row>
		<option>Preserve fewer node names</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable OpenCore Plus hardware evaluation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Verilog Version</option>
		<setting>Verilog_2001</setting>
		<default_value>Verilog_2001</default_value>
	</row>
	<row>
		<option>VHDL Version</option>
		<setting>VHDL93</setting>
		<default_value>VHDL93</default_value>
	</row>
	<row>
		<option>State Machine Processing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Extract Verilog State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Extract VHDL State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>NOT Gate Push-Back</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Power-Up Don&apos;t Care</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Redundant Logic Cells</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Remove Duplicate Registers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore CARRY Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore CASCADE Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore ROW GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>Speed</setting>
		<default_value>Speed</default_value>
	</row>
	<row>
		<option>Allow XOR Gate Usage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Logic Cell Insertion</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>4</setting>
		<default_value>4</default_value>
	</row>
	<row>
		<option>Auto Parallel Expanders</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>100</setting>
		<default_value>100</default_value>
	</row>
</analysis___synthesis_settings>
<compilation_summary>
	<flow_status>Successful - Wed Jan 04 09:38:37 2006</flow_status>
	<quartus_ii_version>4.2 Build 156 11/29/2004 SJ Web Edition</quartus_ii_version>
	<revision_name>Q7230</revision_name>
	<top_level_entity_name>TOP</top_level_entity_name>
	<family>MAX3000A</family>
	<device>EPM3032ALC44-10</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_macrocells>28</total_macrocells>
	<total_pins>19</total_pins>
</compilation_summary>
<compile_id>64C1F317</compile_id>
</talkback>