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📄 c_16450_vhd.htm

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			MSR_EN => MSR_EN,
			CLK => CLK,
			CE => CE,
			INIT => INITIALIZE_CHANGE_DETECTORS(1),
			OUTPUT => DSR_REG,
			DELTA_OUTPUT => DSR_CHANGED
		);

	U2 : ChangeDetector 
		port map (
			INPUT => CTS_TEMP,
			RESET => RESET,
			RD => RD,
			MSR_EN => MSR_EN,
			CLK => CLK,
			CE => CE,
			INIT => INITIALIZE_CHANGE_DETECTORS(1),
			OUTPUT => CTS_REG,
			DELTA_OUTPUT => CTS_CHANGED
		);

	process(CLK, RESET)
	begin
		if (RESET = '0') then
			RI_REG <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				RI_REG <= RI_TEMP;
			end if;
		end if;
	end process;

	process(RESET, RI_CHANGED_RESET, CLK)
	begin
		if ((RESET = '0') or (RI_CHANGED_RESET = '1')) then
			RI_CHANGED <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				RI_CHANGED <= not INITIALIZE_CHANGE_DETECTORS(1) and (RI_CHANGED or (RI_OLD_VALUE and not RI_REG));
			end if;
		end if;
	end process;

	process(RESET, CLK)
	begin
		if (RESET = '0') then
			RI_OLD_VALUE <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				RI_OLD_VALUE <= RI_REG;
			end if;
		end if;
	end process;

	process(RD, RESET, RI_CHANGED)
	begin
		if ((RESET = '0') or (RI_CHANGED = '0')) then
			RI_CHANGED_RESET <= '0';
		elsif (rising_edge(RD)) then
			RI_CHANGED_RESET <= MSR_EN;
		end if;
	end process;
	
	MSR_OUT(7) <= DCD_REG;
	MSR_OUT(6) <= RI_REG;
	MSR_OUT(5) <= DSR_REG;
	MSR_OUT(4) <= CTS_REG;
	MSR_OUT(3) <= DCD_CHANGED;
	MSR_OUT(2) <= RI_CHANGED;
	MSR_OUT(1) <= DSR_CHANGED;
	MSR_OUT(0) <= CTS_CHANGED;

	MODEM_CONTROL_INTERRUPT <= DCD_CHANGED or RI_CHANGED or DSR_CHANGED or CTS_CHANGED;

end architecture;

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {C_16450} architecture {C_16450_arch}}

library IEEE;
use IEEE.std_logic_1164.all;

entity C_16450 is
	port (
		CLK : in std_logic;
		RD : in std_logic;
		WR : in std_logic;
		CE : in std_logic;
		MR : in std_logic;
		CS0 : in std_logic;
		CS1 : in std_logic;
		CS2 : in std_logic;
		CSOUT : out std_logic;
		CTS : in std_logic;
		DCD : in std_logic;
		DSR : in std_logic;
		RI : in std_logic;
		A : in std_logic_vector(2 downto 0);
		DATA_IN : in std_logic_vector(7 downto 0);
		DDIS : out std_logic;
		INT : out std_logic;
		SIN : in std_logic;
		SOUT : out std_logic;
		DTR : out std_logic;
		OUT1 : out std_logic;
		OUT2 : out std_logic;
		RTS : out std_logic;
		DATA_OUT : out std_logic_vector(7 downto 0)
	);
end entity;

--}} End of automatically maintained section

architecture C_16450_arch of C_16450 is
component TransmitterCore is
	port(
		CLK : in std_logic;
		CE : in std_logic;
		BREAK : in std_logic;
		LOOPBACK : in std_logic;
		RESET : in std_logic;
		DATA_IN : in std_logic_vector(7 downto 0);
		WR : in std_logic;
		RD : in std_logic;
		THR_EN : in std_logic;
		IID_EN : in std_logic;
		SERIAL_OUT : out std_logic;
		INTERNAL_SO : out std_logic;
		BITS_COUNT : in std_logic_vector(1 downto 0);
		PARITY_ENABLE : in std_logic;
		PARITY_EVEN_nODD : in std_logic;
		STICK_PARITY : in std_logic;
		TRANSMITTER_INTERRUPT_ACK : in std_logic;
		TRANSMITTER_INTERRUPT : out std_logic;
		LSR_MSB : out std_logic_vector(1 downto 0);
		STOP_BITS : in std_logic
	);
end component;

component ReceiverCore is
	port(
		CLK : in std_logic;
		RESET : in std_logic;
		CE : in std_logic;
		LOOPBACK : in std_logic;
		EXTERNAL_SERIAL_IN : in std_logic;
		INTERNAL_SERIAL_IN : in std_logic;
		RHR_OUT : out std_logic_vector(7 downto 0);
		LSR_OUT : out std_logic_vector(4 downto 0);
		BITS_COUNT : in std_logic_vector(1 downto 0);
		PARITY_ENABLE : in std_logic;
		PARITY_EVEN_nODD : in std_logic;
		STICK_PARITY : in std_logic;
		RD : in std_logic;
		LINE_STATUS_INTERRUPT : out std_logic;
		RECEIVER_INTERRUPT : out std_logic;
		RHR_EN : in std_logic;
		LSR_EN : in std_logic
	);
end component;

component BaudGenerator is
	port(
		RESET : in std_logic;
		CE : in std_logic;
		CE_OUT : out std_logic;
		TRANSMITTER_CE : out std_logic;
		DIV_VAL : in std_logic_vector(15 downto 0);
		CLK : in std_logic
	);
end component;

component ModemControlLogic is
	port(
		CLK : in std_logic;
		RESET : in std_logic;
		CE : in std_logic;
		WR : in std_logic;
		RD : in std_logic;
		DATA_IN : in std_logic_vector(7 downto 0);
		RTS : out std_logic;
		DTR : out std_logic;
		OUT1 : out std_logic;
		OUT2 : out std_logic;
		CTS : in std_logic;
		DSR : in std_logic;
		DCD : in std_logic;
		RI : in std_logic;
		MCR_EN : in std_logic;
		MSR_EN : in std_logic;
		LOOPBACK : out std_logic;
		MODEM_CONTROL_INTERRUPT : out std_logic;
		MCR_OUT : out std_logic_vector(4 downto 0);
		MSR_OUT : out std_logic_vector(7 downto 0)
	);
end component;

component InterruptControlLogic is
	port(
		CLK : in std_logic;
		RESET : in std_logic;
		CE : in std_logic;
		WR : in std_logic;
		RD : in std_logic;
		DATA_IN : in std_logic_vector(7 downto 0);
		IER_EN : in std_logic;
		IID_EN : in std_logic;
		IER_OUT : out std_logic_vector(3 downto 0);
		IID_OUT : out std_logic_vector(2 downto 0);
		TRANSMITTER_INTERRUPT : in std_logic;
		TRANSMITTER_INTERRUPT_ACK : out std_logic;
		RECEIVER_INTERRUPT : in std_logic;
		LINE_STATUS_INTERRUPT : in std_logic;
		MODEM_CONTROL_INTERRUPT : in std_logic;
		INTERRUPT : out std_logic
	);
end component;

component Registers is
	port(
		CS0 : in std_logic;
		CS1 : in std_logic;
		CS2 : in std_logic;
		CSOUT : out std_logic;
		DDIS : out std_logic;
		A : in std_logic_vector(2 downto 0);
		RESET : in std_logic;
		THR_EN : out std_logic;
		RHR_EN : out std_logic;
		IER_EN : out std_logic;
		IID_EN : out std_logic;
		MCR_EN : out std_logic;
		MSR_EN : out std_logic;
		LSR_EN : out std_logic;
		WR : in std_logic;
		RD : in std_logic;
		DATA_IN : in std_logic_vector(7 downto 0);
		DATA_OUT : out std_logic_vector(7 downto 0);
		DIV_REG_OUT : out std_logic_vector(15 downto 0);
		WORD_LEN : out std_logic_vector(1 downto 0);
		RHR : in std_logic_vector(7 downto 0);
		MCR : in std_logic_vector(4 downto 0);
		MSR : in std_logic_vector(7 downto 0);
		LSR_LSB : in std_logic_vector(4 downto 0);
		LSR_MSB : in std_logic_vector(1 downto 0);
		IER : in std_logic_vector(3 downto 0);
		IID : in std_logic_vector(2 downto 0);
		BREAK : out std_logic;
		STICK_PARITY : out std_logic;
		PARITY_EVEN_nODD : out std_logic;
		STOP_BITS : out std_logic;
		PARITY_ENABLE : out std_logic
	);
end component;


signal BITS_COUNT : std_logic_vector (1 downto 0);
signal BREAK : std_logic;
signal CONST_PARITY : std_logic;
signal DIV_VAL : std_logic_vector (15 downto 0);
signal IER_EN : std_logic;
signal IER_OUT : std_logic_vector (3 downto 0);
signal IID_EN : std_logic;
signal IID_OUT : std_logic_vector (2 downto 0);
signal INTERNAL_SERIAL_OUT : std_logic;
signal LINE_STATUS_INTERRUPT : std_logic;
signal LOOPBACK : std_logic;
signal LSR_EN : std_logic;
signal LSR_LSB : std_logic_vector (4 downto 0);
signal LSR_MSB : std_logic_vector (1 downto 0);
signal MCR_EN : std_logic;
signal MCR_OUT : std_logic_vector (4 downto 0);
signal MODEM_CONTROL_INTERRUPT : std_logic;
signal MSR_EN : std_logic;
signal MSR_OUT : std_logic_vector (7 downto 0);
signal PARITY_ENABLE : std_logic;
signal PARITY_TYPE : std_logic;
signal RECEIVER_INTERRUPT : std_logic;
signal RHR_EN : std_logic;
signal RHR_OUT : std_logic_vector (7 downto 0);
signal STOP_BITS : std_logic;
signal THR_EN : std_logic;
signal TRANSMITTER_CE : std_logic;
signal TRANSMITTER_INTERRUPT : std_logic;
signal TRANSMITTER_INTERRUPT_ACK : std_logic;
signal RECEIVER_CE : std_logic;

begin

	U0 : Registers port map(
		CS0 => CS0,
		CS1 => CS1,
		CS2 => CS2,
		CSOUT => CSOUT,
		DDIS => DDIS,
		A => A,
		RESET => MR,
		THR_EN => THR_EN,
		RHR_EN => RHR_EN,
		LSR_EN => LSR_EN,
		IER_EN => IER_EN,
		IID_EN => IID_EN,
		MCR_EN => MCR_EN,
		MSR_EN => MSR_EN,
		WR => WR,
		RD => RD,
		DATA_IN => DATA_IN,
		DATA_OUT => DATA_OUT,
		DIV_REG_OUT => DIV_VAL,
		WORD_LEN => BITS_COUNT,
		RHR => RHR_OUT,
		MCR => MCR_OUT,
		MSR => MSR_OUT,
		LSR_LSB => LSR_LSB,
		LSR_MSB => LSR_MSB,
		IER => IER_OUT,
		IID => IID_OUT,
		BREAK => BREAK,
		STOP_BITS => STOP_BITS,
		STICK_PARITY => CONST_PARITY,
		PARITY_EVEN_nODD => PARITY_TYPE,
		PARITY_ENABLE => PARITY_ENABLE
	);

	U1 : BaudGenerator port map(
		RESET => MR,
		CE => CE,
		CE_OUT => RECEIVER_CE,
		TRANSMITTER_CE => TRANSMITTER_CE,
		DIV_VAL => DIV_VAL,
		CLK => CLK
	);

	U2 : ReceiverCore port map(
		CLK => CLK,
		RESET => MR,
		CE => RECEIVER_CE,
		LOOPBACK => LOOPBACK,
		EXTERNAL_SERIAL_IN => SIN,
		INTERNAL_SERIAL_IN => INTERNAL_SERIAL_OUT,
		RHR_OUT => RHR_OUT,
		LSR_OUT => LSR_LSB,
		BITS_COUNT => BITS_COUNT,
		PARITY_ENABLE => PARITY_ENABLE,
		PARITY_EVEN_nODD => PARITY_TYPE,
		STICK_PARITY => CONST_PARITY,
		RD => RD,
		LINE_STATUS_INTERRUPT => LINE_STATUS_INTERRUPT,
		RECEIVER_INTERRUPT => RECEIVER_INTERRUPT,
		RHR_EN => RHR_EN,
		LSR_EN => LSR_EN
	);

	U3 : TransmitterCore port map(
		CLK => CLK,
		RESET => MR,
		CE => TRANSMITTER_CE,
		BREAK => BREAK,
		LOOPBACK => LOOPBACK,
		DATA_IN => DATA_IN,
		RD => RD,
		WR => WR,
		THR_EN => THR_EN,
		IID_EN => IID_EN,
		SERIAL_OUT => SOUT,
		INTERNAL_SO => INTERNAL_SERIAL_OUT,
		BITS_COUNT => BITS_COUNT,
		PARITY_ENABLE => PARITY_ENABLE,
		PARITY_EVEN_nODD => PARITY_TYPE,
		STICK_PARITY => CONST_PARITY,
		TRANSMITTER_INTERRUPT_ACK => TRANSMITTER_INTERRUPT_ACK,
		TRANSMITTER_INTERRUPT => TRANSMITTER_INTERRUPT,
		LSR_MSB => LSR_MSB,
		STOP_BITS => STOP_BITS
	);

	U4 : InterruptControlLogic port map(
		CLK => CLK,
		RESET => MR,
		CE => CE,
		RD => RD,
		WR => WR,
		DATA_IN => DATA_IN,
		IER_EN => IER_EN,
		IID_EN => IID_EN,
		IER_OUT => IER_OUT,
		IID_OUT => IID_OUT,
		TRANSMITTER_INTERRUPT => TRANSMITTER_INTERRUPT,
		TRANSMITTER_INTERRUPT_ACK => TRANSMITTER_INTERRUPT_ACK,
		RECEIVER_INTERRUPT => RECEIVER_INTERRUPT,
		LINE_STATUS_INTERRUPT => LINE_STATUS_INTERRUPT,
		MODEM_CONTROL_INTERRUPT => MODEM_CONTROL_INTERRUPT,
		INTERRUPT => INT
	);

	U5 : ModemControlLogic port map(
		CLK => CLK,
		RESET => MR,
		CE => CE,
		WR => WR,
		RD => RD,
		DATA_IN => DATA_IN,
		RTS => RTS,
		DTR => DTR,
		OUT1 => OUT1,
		OUT2 => OUT2,
		CTS => CTS,
		DSR => DSR,
		DCD => DCD,
		RI => RI,
		MCR_EN => MCR_EN,
		MSR_EN => MSR_EN,
		LOOPBACK => LOOPBACK,
		MODEM_CONTROL_INTERRUPT => MODEM_CONTROL_INTERRUPT,
		MCR_OUT => MCR_OUT,
		MSR_OUT => MSR_OUT
	);

end architecture;
</PRE></BODY></HTML>
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