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1234 
	end process;

	process(CLK, RESET)
	begin
		if (RESET = '0') then
			TRANSMISSION_IN_PROGRESS <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				if (INTERNAL_START = '1') then
					TRANSMISSION_IN_PROGRESS <= '1';
				elsif (BITS_COUNTER(4 downto 1) = "0000" and CLK_8_CE = '1') then
					TRANSMISSION_IN_PROGRESS <= '0';
				end if;
			end if;
		end if;
	end process;

	process(CLK, RESET)
	begin
		if (RESET = '0') then
			SHIFT_REGISTER <= (others => STOP_BIT_VALUE);
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				if (INTERNAL_START = '1') then
					SHIFT_REGISTER <= DATA_TO_TRANSFER;
				else
					if (CLK_16_CE = '1') then
						SHIFT_REGISTER <= SHIFT_REGISTER(8 downto 0) & STOP_BIT_VALUE;
					end if;
				end if;
			end if;
		end if;
	end process;

	LSR_MSB(1) <= not (TRANSMISSION_IN_PROGRESS or START);
	LSR_MSB(0) <= not START;

	INTERNAL_SO <= BREAK_VALUE when BREAK = '1' else SHIFT_REGISTER(9);

	SERIAL_OUT <= BREAK_VALUE when (BREAK = '1' and LOOPBACK = '0') else '1' when (LOOPBACK = '1') else SHIFT_REGISTER(9);

end architecture;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity BaudGenerator is
	port(
		RESET : in std_logic;
		CE : in std_logic;
		CE_OUT : out std_logic;
		TRANSMITTER_CE : out std_logic;
		DIV_VAL : in std_logic_vector(15 downto 0);
		CLK : in std_logic
	);
end entity;

architecture BaudGenerator_ARCH of BaudGenerator is
signal COUNTER : std_logic_vector(15 downto 0);
signal DIVIDE_BY_ZERO : std_logic;
signal CE_TEMP : std_logic;
signal RELOAD : std_logic;
begin
	process(CLK, RESET)
	begin
		if (RESET = '0') then
			COUNTER <= "0000000000000001";
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				if (RELOAD = '1') then
					COUNTER <= DIV_VAL;
				else
					COUNTER <= COUNTER - 1;
				end if;
			end if;
		end if;
	end process;

	RELOAD <= '1' when COUNTER(15 downto 1) = "000000000000000" else '0';

	process(CLK, RESET)
	begin
		if (RESET = '0') then
			CE_TEMP <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				CE_TEMP <= RELOAD;
			else
				CE_TEMP <= '0';
			end if;
		end if;
	end process;

	process(CLK, RESET)
	begin
		if (RESET = '0') then
			DIVIDE_BY_ZERO <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				if (DIV_VAL = "0000000000000000") then
					DIVIDE_BY_ZERO <= '1';
				else
					DIVIDE_BY_ZERO <= '0';
				end if;
			end if;
		end if;
	end process;

	TRANSMITTER_CE <= CE_TEMP and not DIVIDE_BY_ZERO;

	CE_OUT <= CE_TEMP;

end architecture;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity InterruptControlLogic is
	port(
		CLK : in std_logic;
		RESET : in std_logic;
		CE : in std_logic;
		WR : in std_logic;
		RD : in std_logic;
		DATA_IN : in std_logic_vector(7 downto 0);
		IER_EN : in std_logic;
		IID_EN : in std_logic;
		IER_OUT : out std_logic_vector(3 downto 0);
		IID_OUT : out std_logic_vector(2 downto 0);
		TRANSMITTER_INTERRUPT : in std_logic;
		TRANSMITTER_INTERRUPT_ACK : out std_logic;
		RECEIVER_INTERRUPT : in std_logic;
		LINE_STATUS_INTERRUPT : in std_logic;
		MODEM_CONTROL_INTERRUPT : in std_logic;
		INTERRUPT : out std_logic
	);
end entity;

architecture InterruptControlLogic_ARCH of InterruptControlLogic is
signal IER_3 : STD_LOGIC;
signal IER_2 : STD_LOGIC;
signal IER_1 : STD_LOGIC;
signal IER_0 : STD_LOGIC;
signal IID : STD_LOGIC_VECTOR(2 downto 0);
signal TRANSMITTER_INT : STD_LOGIC;
signal RECEIVER_INT : STD_LOGIC;
signal MODEM_INT : STD_LOGIC;
signal LINE_INT : STD_LOGIC;
signal INTERRUPT_REG : STD_LOGIC;

begin

	process(WR, RESET)
	begin
		if (RESET = '0') then
			IER_3 <= '0';
			IER_2 <= '0';
			IER_1 <= '0';
			IER_0 <= '0';
		elsif (rising_edge(WR)) then
			if (IER_EN = '1') then
			IER_3 <= DATA_IN(3);
			IER_2 <= DATA_IN(2);
			IER_1 <= DATA_IN(1);
			IER_0 <= DATA_IN(0);
			end if;
		end if;
	end process;

	IER_OUT <= IER_3 & IER_2 & IER_1 & IER_0;

	RECEIVER_INT <= RECEIVER_INTERRUPT and IER_0;
	TRANSMITTER_INT <= TRANSMITTER_INTERRUPT and IER_1;
	LINE_INT <= LINE_STATUS_INTERRUPT and IER_2;
	MODEM_INT <= MODEM_CONTROL_INTERRUPT and IER_3;

	process(CLK, RESET)
	begin
		if (RESET = '0') then
			INTERRUPT_REG <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				INTERRUPT_REG <= (TRANSMITTER_INT or MODEM_INT or LINE_INT or RECEIVER_INT);
			end if;
		end if;
	end process;

	INTERRUPT <= INTERRUPT_REG;

	process(RD, RESET)
	begin
		if (RESET = '0') then
			IID <= "001";
		elsif (falling_edge(RD)) then
			if (IID_EN = '1') then
				IID <= (LINE_INT or RECEIVER_INT) & (LINE_INT or (TRANSMITTER_INT and not RECEIVER_INT)) & (not INTERRUPT_REG);
			end if;
		end if;
	end process;

	IID_OUT <= IID;

	process(RD, RESET, TRANSMITTER_INTERRUPT)
	begin
		if ((RESET = '0') or (TRANSMITTER_INTERRUPT = '0')) then
			TRANSMITTER_INTERRUPT_ACK <= '0';
		elsif (rising_edge(RD)) then
			if (IID_EN = '1') then
				if (IID = "010") then
					TRANSMITTER_INTERRUPT_ACK <= '1';
				end if;
			end if;
		end if;
	end process;

end architecture;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity ChangeDetector is
	port(
		RESET : in std_logic;
		RD : in std_logic;
		CE : in std_logic;
		CLK : in std_logic;
		MSR_EN : in std_logic;
		INIT : in std_logic;
		INPUT : in std_logic;
		OUTPUT : out std_logic;
		DELTA_OUTPUT : out std_logic
	);
end entity;

architecture ChangeDetector_ARCH of ChangeDetector is
signal OLD_VALUE : STD_LOGIC;
signal RESET_INPUT_CHANGED : STD_LOGIC;
signal INPUT_CHANGED : STD_LOGIC;
signal REGISTERED_INPUT : STD_LOGIC;
begin

	process(CLK, RESET)
	begin
		if (RESET = '0') then
			REGISTERED_INPUT <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				REGISTERED_INPUT <= INPUT;
			end if;
		end if;
	end process;

	process(CLK, RESET)
	begin
		if (RESET = '0') then
			OLD_VALUE <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				OLD_VALUE <= REGISTERED_INPUT;
			end if;
		end if;
	end process;

	process(RD, RESET, INPUT_CHANGED)
	begin
		if (RESET = '0' or INPUT_CHANGED = '0') then
			RESET_INPUT_CHANGED <= '0';
		elsif (rising_edge(RD)) then
			RESET_INPUT_CHANGED <= MSR_EN;
		end if;
	end process;

	process(CLK, RESET, RESET_INPUT_CHANGED)
	begin
		if (RESET = '0' or RESET_INPUT_CHANGED = '1') then
			INPUT_CHANGED <= '0';
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				INPUT_CHANGED <= not INIT and (INPUT_CHANGED or (OLD_VALUE xor REGISTERED_INPUT));
			end if;
		end if;
	end process;	

	OUTPUT <= REGISTERED_INPUT;

	DELTA_OUTPUT <= INPUT_CHANGED;

end architecture;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity ModemControlLogic is
	port(
		CLK : in std_logic;
		RESET : in std_logic;
		CE : in std_logic;
		WR : in std_logic;
		RD : in std_logic;
		DATA_IN : in std_logic_vector(7 downto 0);
		RTS : out std_logic;
		DTR : out std_logic;
		OUT1 : out std_logic;
		OUT2 : out std_logic;
		CTS : in std_logic;
		DSR : in std_logic;
		DCD : in std_logic;
		RI : in std_logic;
		MCR_EN : in std_logic;
		MSR_EN : in std_logic;
		LOOPBACK : out std_logic;
		MODEM_CONTROL_INTERRUPT : out std_logic;
		MCR_OUT : out std_logic_vector(4 downto 0);
		MSR_OUT : out std_logic_vector(7 downto 0)
	);
end entity;

architecture ModemControlLogic_ARCH of ModemControlLogic is
	component ChangeDetector
	port(
		RESET : in STD_LOGIC;
		RD : in STD_LOGIC;
		MSR_EN : in STD_LOGIC;
		CLK : in STD_LOGIC;
		CE : in STD_LOGIC;
		INIT : in STD_LOGIC;
		INPUT : in STD_LOGIC;
		OUTPUT : out STD_LOGIC;
		DELTA_OUTPUT : out STD_LOGIC);
	end component;

signal MCR_4 : STD_LOGIC;
signal MCR_3 : STD_LOGIC;
signal MCR_2 : STD_LOGIC;
signal MCR_1 : STD_LOGIC;
signal MCR_0 : STD_LOGIC;
signal CTS_CHANGED : STD_LOGIC;
signal DSR_CHANGED : STD_LOGIC;
signal DCD_CHANGED : STD_LOGIC;
signal RI_CHANGED : STD_LOGIC;
signal RI_CHANGED_RESET : STD_LOGIC;

signal CTS_TEMP : STD_LOGIC;
signal DSR_TEMP : STD_LOGIC;
signal DCD_TEMP : STD_LOGIC;
signal RI_TEMP : STD_LOGIC;

signal CTS_REG : STD_LOGIC;
signal DSR_REG : STD_LOGIC;
signal DCD_REG : STD_LOGIC;
signal RI_REG : STD_LOGIC;

signal RI_OLD_VALUE : STD_LOGIC;
signal INITIALIZE_CHANGE_DETECTORS : STD_LOGIC_VECTOR(1 downto 0);

begin

	process(RESET, WR)
	begin
		if (RESET = '0') then
			MCR_4 <= '0';
			MCR_3 <= '0';
			MCR_2 <= '0';
			MCR_1 <= '0';
			MCR_0 <= '0';
		elsif (rising_edge(WR)) then
			if (MCR_EN = '1') then
			MCR_4 <= DATA_IN(4);
			MCR_3 <= DATA_IN(3);
			MCR_2 <= DATA_IN(2);
			MCR_1 <= DATA_IN(1);
			MCR_0 <= DATA_IN(0);
			end if;
		end if;
	end process;

	LOOPBACK <= MCR_4;

	MCR_OUT <= MCR_4 & MCR_3 & MCR_2 & MCR_1 & MCR_0;

	DTR <= not MCR_0 when MCR_4 = '0' else '1';
	RTS <= not MCR_1 when MCR_4 = '0' else '1';
	OUT1 <= not MCR_2 when MCR_4 = '0' else '1';
	OUT2 <= not MCR_3 when MCR_4 = '0' else '1';

	DCD_TEMP <= not DCD when MCR_4 = '0' else MCR_3;
	RI_TEMP <= not RI when MCR_4 = '0' else MCR_2;
	DSR_TEMP <= not DSR when MCR_4 = '0' else MCR_1;
	CTS_TEMP <= not CTS when MCR_4 = '0' else MCR_0;

	process(CLK, RESET)
	begin
		if (RESET = '0') then
			INITIALIZE_CHANGE_DETECTORS <= "11";
		elsif (rising_edge(CLK)) then
			if (CE = '1') then
				INITIALIZE_CHANGE_DETECTORS <= INITIALIZE_CHANGE_DETECTORS(0) & '0';
			end if;
		end if;
	end process;

	U0 : ChangeDetector 
		port map (
			INPUT => DCD_TEMP,
			RESET => RESET,
			RD => RD,
			MSR_EN => MSR_EN,
			CLK => CLK,
			CE => CE,
			INIT => INITIALIZE_CHANGE_DETECTORS(1),
			OUTPUT => DCD_REG,
			DELTA_OUTPUT => DCD_CHANGED
		);

	U1 : ChangeDetector 
		port map (
			INPUT => DSR_TEMP,
			RESET => RESET,
			RD => RD,
1234

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