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// Copyright (c) 2002 by Aldec, Inc. All rights reserved.
//
//-----------------------------------------------------------------------------------
// DESCRIPTION : Component was generated by Aldec IP CORE Generator, version 3.0
// Details:
// C-16450 serial asynchronous transciver
// Blocks included:
// Interrupt Control Logic
// Modem Control Logic
// Baud Generator
// CREATED : 2004-8-31, 22:54:1
//-----------------------------------------------------------------------------------
module Registers (CS0, CS1, CS2, CSOUT, DDIS, A, RESET, THR_EN, RHR_EN, LSR_EN,
IER_EN, IID_EN, MCR_EN, MSR_EN, WR, RD, DATA_IN, DATA_OUT,
DIV_REG_OUT, WORD_LEN, RHR, LSR_LSB, MCR, MSR, LSR_MSB, BREAK,
STOP_BITS, IER, IID, STICK_PARITY, PARITY_EVEN_nODD, PARITY_ENABLE);
input CS0;
wire CS0;
input CS1;
wire CS1;
input CS2;
wire CS2;
output CSOUT;
wire CSOUT;
output DDIS;
wire DDIS;
input [2:0] A;
wire [2:0] A;
input RESET;
wire RESET;
output THR_EN;
wire THR_EN;
output RHR_EN;
wire RHR_EN;
output LSR_EN;
wire LSR_EN;
output IER_EN;
wire IER_EN;
output IID_EN;
wire IID_EN;
output MCR_EN;
wire MCR_EN;
output MSR_EN;
wire MSR_EN;
input WR;
wire WR;
input RD;
wire RD;
input [7:0] DATA_IN;
wire [7:0] DATA_IN;
output [7:0] DATA_OUT;
reg [7:0] DATA_OUT;
output [15:0] DIV_REG_OUT;
wire [15:0] DIV_REG_OUT;
output [1:0] WORD_LEN;
wire [1:0] WORD_LEN;
input [7:0] RHR;
wire [7:0] RHR;
input [4:0] LSR_LSB;
wire [4:0] LSR_LSB;
input [4:0] MCR;
wire [4:0] MCR;
input [7:0] MSR;
wire [7:0] MSR;
input [1:0] LSR_MSB;
wire [1:0] LSR_MSB;
output BREAK;
wire BREAK;
output STOP_BITS;
wire STOP_BITS;
input [3:0] IER;
wire [3:0] IER;
input [2:0] IID;
wire [2:0] IID;
output STICK_PARITY;
wire STICK_PARITY;
output PARITY_EVEN_nODD;
wire PARITY_EVEN_nODD;
output PARITY_ENABLE;
wire PARITY_ENABLE;
reg [7:0] LSB;
reg [7:0] MSB;
reg [7:0] LCR;
reg [7:0] SCRATCH;
wire CS;
wire DRAB;
wire THR_SELECT;
wire RHR_SELECT;
wire DIV_LSB_SELECT;
wire DIV_MSB_SELECT;
wire IER_SELECT;
wire IID_SELECT;
wire LCR_SELECT;
wire MCR_SELECT;
wire LSR_SELECT;
wire MSR_SELECT;
wire SCRATCH_SELECT;
`define RHR_ADDRESS 3'b000
`define THR_ADDRESS 3'b000
`define DIV_LSB_ADDRESS 3'b000
`define DIV_MSB_ADDRESS 3'b001
`define IER_ADDRESS 3'b001
`define IID_ADDRESS 3'b010
`define LCR_ADDRESS 3'b011
`define MCR_ADDRESS 3'b100
`define LSR_ADDRESS 3'b101
`define MSR_ADDRESS 3'b110
`define SCRATCH_ADDRESS 3'b111
assign CS = CS0 && CS1 && !CS2;
assign DDIS = !RD && CS;
assign CSOUT = CS;
assign THR_SELECT = (A == `THR_ADDRESS && DRAB == 1'b0 && CS == 1'b1) ? 1'b1 : 1'b0;
assign RHR_SELECT = (A == `RHR_ADDRESS && DRAB == 1'b0 && CS == 1'b1) ? 1'b1 : 1'b0;
assign DIV_LSB_SELECT = (A == `DIV_LSB_ADDRESS && DRAB == 1'b1 && CS == 1'b1) ? 1'b1 : 1'b0;
assign DIV_MSB_SELECT = (A == `DIV_MSB_ADDRESS && DRAB == 1'b1 && CS == 1'b1) ? 1'b1 : 1'b0;
assign IER_SELECT = (A == `IER_ADDRESS && DRAB == 1'b0 && CS == 1'b1) ? 1'b1 : 1'b0;
assign IID_SELECT = (A == `IID_ADDRESS && CS == 1'b1) ? 1'b1 : 1'b0;
assign LCR_SELECT = (A == `LCR_ADDRESS && CS == 1'b1) ? 1'b1 : 1'b0;
assign MCR_SELECT = (A == `MCR_ADDRESS && CS == 1'b1) ? 1'b1 : 1'b0;
assign LSR_SELECT = (A == `LSR_ADDRESS && CS == 1'b1) ? 1'b1 : 1'b0;
assign MSR_SELECT = (A == `MSR_ADDRESS && CS == 1'b1) ? 1'b1 : 1'b0;
assign SCRATCH_SELECT = (A == `SCRATCH_ADDRESS && CS == 1'b1) ? 1'b1 : 1'b0;
assign THR_EN = THR_SELECT;
assign RHR_EN = RHR_SELECT;
assign IER_EN = IER_SELECT;
assign IID_EN = IID_SELECT;
assign MCR_EN = MCR_SELECT;
assign LSR_EN = LSR_SELECT;
assign MSR_EN = MSR_SELECT;
always @(posedge WR or negedge RESET)
if (RESET == 1'b0)
LSB <= 8'b00000001;
else if (DIV_LSB_SELECT == 1'b1)
LSB <= DATA_IN;
always @(posedge WR or negedge RESET)
if (RESET == 1'b0)
MSB <= 8'b00000000;
else if (DIV_MSB_SELECT == 1'b1)
MSB <= DATA_IN;
assign DIV_REG_OUT = {MSB, LSB};
always @(posedge WR or negedge RESET)
if (RESET == 1'b0)
SCRATCH <= 8'b00000000;
else if (SCRATCH_SELECT == 1'b1)
SCRATCH <= DATA_IN;
always @(posedge WR or negedge RESET)
if (RESET == 1'b0)
LCR <= 8'b00011000;
else if (LCR_SELECT == 1'b1)
LCR <= DATA_IN;
assign WORD_LEN = LCR[1:0];
assign DRAB = LCR[7];
assign BREAK = LCR[6];
assign STOP_BITS = LCR[2];
assign PARITY_ENABLE = LCR[3];
assign PARITY_EVEN_nODD = LCR[4];
assign STICK_PARITY = LCR[5];
always @(A or LCR or SCRATCH or RHR or LSR_LSB or DRAB or LSB or MSB or LSR_MSB or IER or IID or MCR or MSR)
case (A)
`RHR_ADDRESS :
if (DRAB == 1'b0)
DATA_OUT = RHR;
else
DATA_OUT = LSB;
`IER_ADDRESS :
if (DRAB == 1'b0)
DATA_OUT = {4'b0000, IER};
else
DATA_OUT = MSB;
`IID_ADDRESS : DATA_OUT = {5'b00000, IID};
`LCR_ADDRESS : DATA_OUT = LCR;
`MCR_ADDRESS : DATA_OUT = {3'b000, MCR};
`LSR_ADDRESS : DATA_OUT = {1'b0, LSR_MSB, LSR_LSB};
`MSR_ADDRESS : DATA_OUT = MSR;
`SCRATCH_ADDRESS : DATA_OUT = SCRATCH;
default : DATA_OUT = 8'b00000000;
endcase
endmodule
module ReceiverCore (CLK, RESET, CE, LOOPBACK, INTERNAL_SERIAL_IN, EXTERNAL_SERIAL_IN,
RHR_OUT, LSR_OUT, BITS_COUNT, PARITY_ENABLE, PARITY_EVEN_nODD,
STICK_PARITY, RD, LINE_STATUS_INTERRUPT, RECEIVER_INTERRUPT, RHR_EN,
LSR_EN);
input CLK;
wire CLK;
input RESET;
wire RESET;
input CE;
wire CE;
input LOOPBACK;
wire LOOPBACK;
input INTERNAL_SERIAL_IN;
wire INTERNAL_SERIAL_IN;
input EXTERNAL_SERIAL_IN;
wire EXTERNAL_SERIAL_IN;
output [7:0] RHR_OUT;
wire [7:0] RHR_OUT;
output [4:0] LSR_OUT;
wire [4:0] LSR_OUT;
input [1:0] BITS_COUNT;
wire [1:0] BITS_COUNT;
input PARITY_ENABLE;
wire PARITY_ENABLE;
input PARITY_EVEN_nODD;
wire PARITY_EVEN_nODD;
input STICK_PARITY;
wire STICK_PARITY;
input RD;
wire RD;
output LINE_STATUS_INTERRUPT;
wire LINE_STATUS_INTERRUPT;
output RECEIVER_INTERRUPT;
wire RECEIVER_INTERRUPT;
input RHR_EN;
wire RHR_EN;
input LSR_EN;
wire LSR_EN;
`define IDLE_STATE 4'b0000
`define START_STATE 4'b0001
`define BIT0_STATE 4'b1001
`define BIT1_STATE 4'b1011
`define BIT2_STATE 4'b1010
`define BIT3_STATE 4'b1000
`define BIT4_STATE 4'b1100
`define BIT5_STATE 4'b1101
`define BIT6_STATE 4'b1111
`define BIT7_STATE 4'b1110
`define PARITY_STATE 4'b0101
`define STOP_STATE 4'b0111
`define BREAK_STATE 4'b0011
wire RECEIVING_DATA_BIT;
wire RECEIVING_PARITY_BIT;
wire RECEIVING_STOP_BIT;
wire RECEIVER_IDLE;
wire RECEIVER_IDLE_BREAK;
reg [3:0] RECEIVER_STATE;
reg [7:0] SHIFT_REGISTER;
wire [7:0] SHIFT_REGISTER_INPUT;
reg [7:0] RECEIVER_HOLDING_REGISTER;
reg RHR_FULL;
reg RESET_RHR_FULL;
wire RESET_RHR_FULL_RESET;
wire RHR_FULL_RESET;
wire RHR_WRITE_ENABLE;
wire CALCULATED_PARITY;
reg PARITY_REGISTER;
reg START_CONFIRMED;
reg [3:0] CLOCK_DIVIDER;
wire RELOAD_COUNTER;
wire NEXT_STATE;
reg BREAK_DETECTED;
wire BREAK_DETECTED_RESET;
reg RESET_BREAK_DETECTED;
wire RESET_BREAK_DETECTED_RESET;
reg BREAK_DETECTOR;
wire CATCH_ENABLE;
reg RESET_FRAME_ERROR;
wire RESET_FRAME_ERROR_RESET;
reg FRAME_ERROR;
wire FRAME_ERROR_RESET;
reg RESET_OVERRUN_ERROR;
wire RESET_OVERRUN_ERROR_RESET;
reg OVERRUN_ERROR;
wire OVERRUN_ERROR_RESET;
reg RESET_PARITY_ERROR;
wire RESET_PARITY_ERROR_RESET;
reg PARITY_ERROR;
wire PARITY_ERROR_RESET;
wire PARITY_OK;
reg STOP_BIT;
reg SERIAL_IN;
assign RECEIVING_DATA_BIT = RECEIVER_STATE[3];
assign RECEIVING_PARITY_BIT = (RECEIVER_STATE[3:1] == 3'b010) ? 1'b1 : 1'b0;
assign RECEIVING_STOP_BIT = (RECEIVER_STATE[3:1] == 3'b011) ? 1'b1 : 1'b0;
assign RECEIVER_IDLE = !(RECEIVER_STATE[3] || RECEIVER_STATE[0]);
assign RECEIVER_IDLE_BREAK = ((RECEIVER_STATE == 4'b0011) || (RECEIVER_STATE == 4'b0000)) ? 1'b1 : 1'b0;
always @(posedge CLK or negedge RESET)
if (RESET == 1'b0)
SERIAL_IN <= 1'b1;
else if (CE == 1'b1)
if (LOOPBACK == 1'b1)
SERIAL_IN <= INTERNAL_SERIAL_IN;
else
SERIAL_IN <= EXTERNAL_SERIAL_IN;
always @(posedge CLK or negedge RESET)
if (RESET == 1'b0)
STOP_BIT <= 1'b1;
else if ((CATCH_ENABLE == 1'b1) && (RECEIVING_STOP_BIT == 1'b1))
STOP_BIT <= SERIAL_IN;
always @(posedge CLK or negedge RESET)
if (RESET == 1'b0)
PARITY_REGISTER <= 1'b0;
else if (CATCH_ENABLE == 1'b1)
if (PARITY_ENABLE == 1'b0)
PARITY_REGISTER <= 1'b0;
else if (RECEIVING_PARITY_BIT == 1'b1)
PARITY_REGISTER <= SERIAL_IN;
assign RESET_BREAK_DETECTED_RESET = ((RESET == 1'b0) || (BREAK_DETECTED == 1'b0)) ? 1'b1 : 1'b0;
always @(posedge RD or posedge RESET_BREAK_DETECTED_RESET)
if (RESET_BREAK_DETECTED_RESET == 1'b1)
RESET_BREAK_DETECTED <= 1'b0;
else
RESET_BREAK_DETECTED <= LSR_EN;
assign BREAK_DETECTED_RESET = ((RESET == 1'b0) || (RESET_BREAK_DETECTED == 1'b1)) ? 1'b1 : 1'b0;
always @(posedge CLK or posedge BREAK_DETECTED_RESET)
if (BREAK_DETECTED_RESET == 1'b1)
BREAK_DETECTED <= 1'b0;
else if ((NEXT_STATE == 1'b1) && (RECEIVING_STOP_BIT == 1'b1))
BREAK_DETECTED <= BREAK_DETECTED || !(BREAK_DETECTOR || STOP_BIT || PARITY_REGISTER);
always @(posedge CLK or negedge RESET)
if (RESET == 1'b0)
BREAK_DETECTOR <= 1'b0;
else if (CE == 1'b1)
if (RECEIVING_DATA_BIT == 1'b1)
BREAK_DETECTOR <= (BREAK_DETECTOR || SERIAL_IN);
else if (RECEIVER_IDLE_BREAK == 1'b1)
BREAK_DETECTOR <= 1'b0;
always @(posedge CLK or negedge RESET)
if (RESET == 1'b0)
START_CONFIRMED <= 1'b0;
else if (CATCH_ENABLE == 1'b1)
START_CONFIRMED <= !SERIAL_IN;
assign SHIFT_REGISTER_INPUT[7] = BITS_COUNT[0] && BITS_COUNT[1] && SERIAL_IN;
assign SHIFT_REGISTER_INPUT[6] = BITS_COUNT[1] && ((BITS_COUNT[0] && SHIFT_REGISTER[7]) || (!BITS_COUNT[0] && SERIAL_IN));
assign SHIFT_REGISTER_INPUT[5] = (BITS_COUNT[1] && SHIFT_REGISTER[6]) || (!BITS_COUNT[1] && BITS_COUNT[0] && SERIAL_IN);
assign SHIFT_REGISTER_INPUT[4] = (!BITS_COUNT[0] && !BITS_COUNT[1] && SERIAL_IN) || ((BITS_COUNT[0] || BITS_COUNT[1]) && SHIFT_REGISTER[5]);
assign SHIFT_REGISTER_INPUT[3:0] = SHIFT_REGISTER[4:1];
always @(posedge CLK or negedge RESET)
if (RESET == 1'b0)
SHIFT_REGISTER <= 8'b00000000;
else if ((CATCH_ENABLE == 1'b1) && (RECEIVING_DATA_BIT == 1'b1))
SHIFT_REGISTER <= SHIFT_REGISTER_INPUT;
assign RESET_FRAME_ERROR_RESET = ((RESET == 1'b0) || (FRAME_ERROR == 1'b0)) ? 1'b1 : 1'b0;
always @(posedge RD or posedge RESET_FRAME_ERROR_RESET)
if (RESET_FRAME_ERROR_RESET == 1'b1)
RESET_FRAME_ERROR <= 1'b0;
else
RESET_FRAME_ERROR <= LSR_EN;
assign FRAME_ERROR_RESET = ((RESET == 1'b0) || (RESET_FRAME_ERROR == 1'b1)) ? 1'b1 : 1'b0;
always @(posedge CLK or posedge FRAME_ERROR_RESET)
if (FRAME_ERROR_RESET == 1'b1)
FRAME_ERROR <= 1'b0;
else if (CE == 1'b1)
if (RHR_WRITE_ENABLE == 1'b1)
FRAME_ERROR <= !STOP_BIT;
assign RESET_OVERRUN_ERROR_RESET = ((RESET == 1'b0) || (OVERRUN_ERROR == 1'b0)) ? 1'b1 : 1'b0;
always @(posedge RD or posedge RESET_OVERRUN_ERROR_RESET)
if (RESET_OVERRUN_ERROR_RESET == 1'b1)
RESET_OVERRUN_ERROR <= 1'b0;
else
RESET_OVERRUN_ERROR <= LSR_EN;
assign OVERRUN_ERROR_RESET = ((RESET == 1'b0) || (RESET_OVERRUN_ERROR == 1'b1)) ? 1'b1 : 1'b0;
always @(posedge CLK or posedge OVERRUN_ERROR_RESET)
if (OVERRUN_ERROR_RESET == 1'b1)
OVERRUN_ERROR <= 1'b0;
else if (CE == 1'b1)
if (RHR_WRITE_ENABLE == 1'b1)
OVERRUN_ERROR <= RHR_FULL;
assign RHR_WRITE_ENABLE = NEXT_STATE && RECEIVING_STOP_BIT;
always @(posedge CLK or negedge RESET)
if (RESET == 1'b0)
RECEIVER_HOLDING_REGISTER <= 8'b00000000;
else if ((CE == 1'b1) && (RHR_WRITE_ENABLE == 1'b1))
RECEIVER_HOLDING_REGISTER <= SHIFT_REGISTER;
assign RHR_OUT = RECEIVER_HOLDING_REGISTER;
assign RHR_FULL_RESET = ((RESET == 1'b0) || (RESET_RHR_FULL == 1'b1)) ? 1'b1 : 1'b0;
always @(posedge CLK or posedge RHR_FULL_RESET)
if (RHR_FULL_RESET == 1'b1)
RHR_FULL <= 1'b0;
else if ((CE == 1'b1) && (RHR_WRITE_ENABLE == 1'b1))
RHR_FULL <= 1'b1;
assign RECEIVER_INTERRUPT = RHR_FULL;
assign RESET_RHR_FULL_RESET = ((RESET == 1'b0) || (RHR_FULL == 1'b0)) ? 1'b1 : 1'b0;
always @(posedge RD or posedge RESET_RHR_FULL_RESET)
if (RESET_RHR_FULL_RESET == 1'b1)
RESET_RHR_FULL <= 1'b0;
else
RESET_RHR_FULL <= RHR_EN;
assign CALCULATED_PARITY = (STICK_PARITY == 1'b0) ? (!PARITY_EVEN_nODD ^ SHIFT_REGISTER[7] ^ SHIFT_REGISTER[6] ^
SHIFT_REGISTER[5] ^ SHIFT_REGISTER[4] ^ SHIFT_REGISTER[3] ^
SHIFT_REGISTER[2] ^ SHIFT_REGISTER[1] ^ SHIFT_REGISTER[0]) : !PARITY_EVEN_nODD;
assign PARITY_OK = (!(PARITY_REGISTER ^ CALCULATED_PARITY) || !PARITY_ENABLE);
assign RESET_PARITY_ERROR_RESET = ((RESET == 1'b0) || (PARITY_ERROR == 1'b0)) ? 1'b1 : 1'b0;
always @(posedge RD or posedge RESET_PARITY_ERROR_RESET)
if(RESET_PARITY_ERROR_RESET == 1'b1)
RESET_PARITY_ERROR <= 1'b0;
else
RESET_PARITY_ERROR <= LSR_EN;
assign PARITY_ERROR_RESET = ((RESET == 1'b0) || (RESET_PARITY_ERROR == 1'b1)) ? 1'b1 : 1'b0;
always @(posedge CLK or posedge PARITY_ERROR_RESET)
if (PARITY_ERROR_RESET == 1'b1)
PARITY_ERROR <= 1'b0;
else if (CE == 1'b1)
if (RHR_WRITE_ENABLE == 1'b1)
PARITY_ERROR <= !PARITY_OK;
assign RELOAD_COUNTER = RECEIVER_IDLE;
always @(posedge CLK or negedge RESET)
if (RESET == 1'b0)
CLOCK_DIVIDER <= 4'b0000;
else if (CE == 1'b1)
if (RELOAD_COUNTER == 1'b1)
CLOCK_DIVIDER <= 4'b0000;
else
CLOCK_DIVIDER <= CLOCK_DIVIDER + 1;
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