mul.vhd

ＶＨＤＬ 在ＭＡＸＰＬＵＳ环境下运行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity mul is
  port(
	sel:	in std_logic;
	BCD:	in std_logic_vector(15 downto 0);
	KeyDis:	in std_logic_vector(7 downto 0);
	outdis:	out std_logic_vector(15 downto 0));
  end mul;

  architecture arch of mul is
  BEGIN
	WITH sel SELECT
	  outdis(7 downto 0) <= BCD(7 downto 0) WHEN '1',
		 		  		    KeyDis(7 downto 0) WHEN OTHERS;
	WITH sel SELECT
	  outdis(15 downto 8) <= BCD(15 downto 8) WHEN '1',
		 		  		     "11111111" WHEN OTHERS;
  END arch;