add.vhd

ＶＨＤＬ 在ＭＡＸＰＬＵＳ环境下运行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity add is
  port(
	clk:in std_logic;
	Q:in std_logic_vector(7 downto 0);
	KEYdata:in integer range 0 to 255;
	resu:out integer range 0 to 16383);
  end add;

  architecture arch of add is
  BEGIN
    PROCESS(clk)
	BEGIN
	  if(clk'event and clk = '1') then
		resu <= CONV_INTEGER(Q) + KEYdata;
	  end if;
	END PROCESS;
  END arch;