📄 adeled.rpt
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Device-Specific Information: c:\2003(edapro dp240)\altera7128\add_t\adeled.rpt
adeled
** EQUATIONS **
num0 : INPUT;
num1 : INPUT;
num2 : INPUT;
num3 : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC7_A22;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC2_A22;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC1_A22;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC7_A21;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC3_A21;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC5_A22;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC1_A23;
-- Node name is ':91'
-- Equation name is '_LC8_A22', type is buried
!_LC8_A22 = _LC8_A22~NOT;
_LC8_A22~NOT = LCELL( _EQ001);
_EQ001 = !num1
# num0
# !num3
# num2;
-- Node name is ':127'
-- Equation name is '_LC6_A21', type is buried
!_LC6_A21 = _LC6_A21~NOT;
_LC6_A21~NOT = LCELL( _EQ002);
_EQ002 = !num1
# !num0
# num3
# !num2;
-- Node name is ':163'
-- Equation name is '_LC2_A23', type is buried
!_LC2_A23 = _LC2_A23~NOT;
_LC2_A23~NOT = LCELL( _EQ003);
_EQ003 = num1
# num0
# num3
# !num2;
-- Node name is ':199'
-- Equation name is '_LC2_A21', type is buried
!_LC2_A21 = _LC2_A21~NOT;
_LC2_A21~NOT = LCELL( _EQ004);
_EQ004 = num1
# !num0
# num3
# num2;
-- Node name is ':211'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ005);
_EQ005 = !num0 & !num1 & !num2 & !num3;
-- Node name is ':214'
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = LCELL( _EQ006);
_EQ006 = !num0 & num1
# num1 & !num3
# !num0 & num3
# !num1 & !num2 & num3
# num0 & num2 & !num3
# !num0 & !num2;
-- Node name is ':262'
-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = LCELL( _EQ007);
_EQ007 = num0 & !num1 & num3
# !num1 & !num2
# !num0 & !num1 & !num3
# !num0 & !num2
# num0 & num1 & !num3;
-- Node name is ':310'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = LCELL( _EQ008);
_EQ008 = num2 & !num3
# !num2 & num3
# !num1 & !num2
# num0 & !num1
# !num1 & !num3
# num0 & !num3;
-- Node name is ':325'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = LCELL( _EQ009);
_EQ009 = num0 & num1 & !num2 & num3
# !num0 & num2 & num3
# !num1 & num2 & num3;
-- Node name is ':334'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = LCELL( _EQ010);
_EQ010 = _LC4_A22
# _LC6_A22 & !_LC8_A22;
-- Node name is ':351'
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = LCELL( _EQ011);
_EQ011 = !_LC2_A23 & _LC5_A21
# !_LC2_A23 & _LC3_A22 & !_LC6_A21;
-- Node name is ':358'
-- Equation name is '_LC7_A21', type is buried
_LC7_A21 = LCELL( _EQ012);
_EQ012 = !_LC2_A21 & _LC4_A21
# !_LC2_A21 & _LC8_A21
# _LC1_A21;
-- Node name is ':400'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = LCELL( _EQ013);
_EQ013 = num1 & !num2 & num3
# !num0 & num3
# !num0 & num1
# !num1 & num2 & num3;
-- Node name is ':406'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ014);
_EQ014 = _LC1_A21
# !_LC2_A21 & _LC3_A23;
-- Node name is '~430~1'
-- Equation name is '~430~1', location is LC4_A22, type is buried.
-- synthesized logic cell
_LC4_A22 = LCELL( _EQ015);
_EQ015 = !num1 & !num2 & num3;
-- Node name is '~442~1'
-- Equation name is '~442~1', location is LC5_A21, type is buried.
-- synthesized logic cell
_LC5_A21 = LCELL( _EQ016);
_EQ016 = num0 & !num1 & num2 & !num3
# !num0 & num1 & num2 & !num3;
-- Node name is ':454'
-- Equation name is '_LC5_A22', type is buried
_LC5_A22 = LCELL( _EQ017);
_EQ017 = !num1 & num2 & !num3
# !num0 & num2
# !num0 & num3
# !num0 & !num1
# !num2 & num3;
-- Node name is '~496~1'
-- Equation name is '~496~1', location is LC4_A21, type is buried.
-- synthesized logic cell
_LC4_A21 = LCELL( _EQ018);
_EQ018 = num1 & !num2 & !num3;
-- Node name is ':504'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ019);
_EQ019 = !num0 & num2 & !num3
# !num1 & num2 & !num3
# num1 & !num2
# !num2 & num3
# !num0 & num1
# num0 & !num1 & num2;
Project Information c:\2003(edapro dp240)\altera7128\add_t\adeled.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 23,301K
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