binbcd.vhd

ＶＨＤＬ 在ＭＡＸＰＬＵＳ环境下运行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;

ENTITY binbcd IS  
    PORT ( result 	: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
           clk,reset: IN STD_LOGIC;
--		   qu       : out STD_LOGIC_VECTOR(8 DOWNTO 0);
           bcd 		: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END binbcd;

ARCHITECTURE dff8 OF binbcd IS
SIGNAL nu : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL de : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL clkD: STD_LOGIC;
SIGNAL  qu : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL  re : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
    U1 : divide 
         GENERIC MAP(WIDTH_Q=>12,WIDTH_N=>14,
                     WIDTH_D=>10,WIDTH_R=>10,
                     WIDTH_D_MIN=>3,PIPELINE_DELAY=>0,
						LPM_PIPELINE=>1)
            PORT MAP(numerator=>nu,denominator=>de,--"1111101000",
                      clock=>clkD,
                      quotient=>qu,remainder=>re);
  PROCESS(clk,reset)
  VARIABLE i:INTEGER RANGE 0 TO 6;
  VARIABLE mid:STD_LOGIC_VECTOR(15 DOWNTO 0);
  BEGIN
	if(reset = '0') then
	  i := 0;
	  clkD <= '0';
    elsif(clk'event and clk = '1') then
	  CASE i IS
		WHEN 0 =>
	  			  nu <= result;
	  			  de <= "1111101000";
		WHEN 1 =>
			  	  clkD <= '1';
		WHEN 2 =>
				  mid(15 downto 12) := qu(3 downto 0);
				  nu(9 downto 0) <= re;
				  nu(13 downto 10) <= "00000";  
				  de <= "0001100100";
			  	  clkD <= '0';
		WHEN 3 =>
			  	  clkD <= '1';
		WHEN 4 =>
				  mid(11 downto 8) := qu(3 downto 0);
				  nu(9 downto 0) <= re;
				  nu(13 downto 10) <= "00000";  
				  de <= "0000001010";
			  	  clkD <= '0';
		WHEN 5 =>
			  	  clkD <= '1';
		WHEN OTHERS =>
				  mid(7 downto 4) := qu(3 downto 0);
				  mid(3 downto 0) := re(3 downto 0);
			  	  clkD <= '0';
				  bcd(15 downto 0) <= mid(15 downto 0);
	  END CASE;
	  i := i+1;
	end if;
  END PROCESS;
END;