📄 adder.rpt
字号:
D: 0 0 0 0 0 0 0 0 6 0 8 6 8 1 0 8 0 0 0 8 0 0 0 0 0 0 0 1 0 1 0 8 0 0 0 0 8 63/0
E: 8 0 8 0 0 8 8 0 0 0 6 8 3 8 8 0 8 8 0 0 8 8 6 3 8 0 0 0 0 3 0 0 5 8 8 0 8 146/0
F: 0 0 0 0 0 8 7 8 8 0 8 8 7 0 5 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67/0
Total: 24 8 16 6 7 18 17 9 15 8 26 23 20 19 21 9 16 28 0 8 8 16 6 3 14 8 1 9 16 19 8 16 14 22 13 15 24 510/0
Device-Specific Information: c:\acex 1k demo\1k30_208_vhdl\demo20\adder.rpt
adder
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
78 - - - -- INPUT G ^ 0 0 0 0 CLK1KHz
80 - - - -- INPUT G ^ 0 0 0 0 CLK8Hz
79 - - - -- INPUT G ^ 0 0 0 0 CLK10KHz
54 - - - 35 BIDIR ^ 0 1 0 4 Q0
55 - - - 34 BIDIR ^ 0 1 0 3 Q1
56 - - - 33 BIDIR ^ 0 1 0 3 Q2
57 - - - 32 BIDIR ^ 0 1 0 3 Q3
58 - - - 31 BIDIR ^ 0 1 0 3 Q4
60 - - - 30 BIDIR ^ 0 1 0 3 Q5
61 - - - 29 BIDIR ^ 0 1 0 3 Q6
62 - - - 28 BIDIR ^ 0 1 0 3 Q7
85 - - - 16 INPUT ^ 0 0 0 134 RESET
68 - - - 24 INPUT ^ 0 0 0 4 RL0
69 - - - 23 INPUT ^ 0 0 0 5 RL1
70 - - - 22 INPUT ^ 0 0 0 4 RL2
71 - - - 21 INPUT ^ 0 0 0 3 RL3
73 - - - 20 INPUT ^ 0 0 0 5 RL4
74 - - - 20 INPUT ^ 0 0 0 5 RL5
75 - - - 19 INPUT ^ 0 0 0 5 RL6
83 - - - 17 INPUT ^ 0 0 0 4 RL7
39 - - E -- INPUT ^ 0 0 0 0 SW1
40 - - E -- INPUT ^ 0 0 0 0 SW2
41 - - E -- INPUT ^ 0 0 0 0 SW3
44 - - F -- INPUT ^ 0 0 0 0 SW4
45 - - F -- INPUT ^ 0 0 0 0 SW5
46 - - F -- INPUT ^ 0 0 0 0 SW6
47 - - F -- INPUT ^ 0 0 0 0 SW7
53 - - - 36 INPUT ^ 0 0 0 0 SW8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\acex 1k demo\1k30_208_vhdl\demo20\adder.rpt
adder
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
86 - - - 15 OUTPUT 0 1 0 0 A
87 - - - 14 OUTPUT 0 1 0 0 B
88 - - - 14 OUTPUT 0 1 0 0 C
89 - - - 13 OUTPUT 0 1 0 0 D
90 - - - 12 OUTPUT 0 1 0 0 E
92 - - - 11 OUTPUT 0 1 0 0 F
93 - - - 10 OUTPUT 0 1 0 0 G
170 - - - 11 OUTPUT 0 1 0 0 KB0
54 - - - 35 TRI 0 1 0 4 Q0
55 - - - 34 TRI 0 1 0 3 Q1
56 - - - 33 TRI 0 1 0 3 Q2
57 - - - 32 TRI 0 1 0 3 Q3
58 - - - 31 TRI 0 1 0 3 Q4
60 - - - 30 TRI 0 1 0 3 Q5
61 - - - 29 TRI 0 1 0 3 Q6
62 - - - 28 TRI 0 1 0 3 Q7
172 - - - 12 OUTPUT 0 1 0 0 RAM_RD
173 - - - 13 OUTPUT 0 1 0 0 RAM_WR
174 - - - 14 OUTPUT 0 1 0 0 SS0
175 - - - 14 OUTPUT 0 1 0 0 SS1
176 - - - 15 OUTPUT 0 0 0 0 SS2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\acex 1k demo\1k30_208_vhdl\demo20\adder.rpt
adder
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - E 36 OR2 0 4 0 2 |ADD:41|LPM_ADD_SUB:125|addcore:adder|pcarry1
- 2 - E 22 OR2 0 3 0 2 |ADD:41|LPM_ADD_SUB:125|addcore:adder|pcarry2
- 4 - E 23 OR2 0 3 0 2 |ADD:41|LPM_ADD_SUB:125|addcore:adder|pcarry3
- 1 - A 29 OR2 0 3 0 2 |ADD:41|LPM_ADD_SUB:125|addcore:adder|pcarry4
- 6 - A 30 OR2 0 3 0 2 |ADD:41|LPM_ADD_SUB:125|addcore:adder|pcarry5
- 8 - A 30 OR2 0 3 0 2 |ADD:41|LPM_ADD_SUB:125|addcore:adder|pcarry6
- 4 - F 11 DFFE 0 4 0 1 |ADD:41|:28
- 8 - F 11 DFFE 0 4 0 1 |ADD:41|:30
- 2 - A 30 DFFE 0 4 0 1 |ADD:41|:32
- 6 - A 29 DFFE 0 4 0 1 |ADD:41|:34
- 8 - A 29 DFFE 0 4 0 1 |ADD:41|:36
- 1 - E 23 DFFE 0 4 0 1 |ADD:41|:38
- 4 - E 22 DFFE 0 4 0 1 |ADD:41|:40
- 5 - E 21 DFFE 0 5 0 1 |ADD:41|:42
- 7 - E 21 DFFE 0 3 0 1 |ADD:41|:44
- 2 - D 09 AND2 s 0 2 0 1 |ADELED:43|~55~1
- 8 - D 11 AND2 0 3 0 1 |ADELED:43|:70
- 6 - D 09 OR2 ! 0 4 0 1 |ADELED:43|:91
- 1 - D 16 AND2 0 4 0 2 |ADELED:43|:115
- 3 - D 16 OR2 ! 0 4 0 3 |ADELED:43|:127
- 4 - D 16 AND2 0 4 0 2 |ADELED:43|:139
- 2 - D 11 AND2 0 4 0 2 |ADELED:43|:151
- 5 - D 11 OR2 s 0 2 0 2 |ADELED:43|~154~1
- 4 - D 11 OR2 ! 0 4 0 3 |ADELED:43|:163
- 3 - D 12 AND2 0 4 0 2 |ADELED:43|:175
- 4 - D 12 AND2 0 4 0 2 |ADELED:43|:187
- 1 - D 12 OR2 s 0 2 0 2 |ADELED:43|~190~1
- 6 - D 16 OR2 ! 0 4 0 3 |ADELED:43|:199
- 7 - D 16 AND2 0 4 0 3 |ADELED:43|:211
- 2 - D 16 OR2 0 4 1 0 |ADELED:43|:214
- 2 - B 14 OR2 0 4 1 0 |ADELED:43|:262
- 6 - D 11 OR2 s 0 2 0 1 |ADELED:43|~301~1
- 1 - B 14 OR2 0 4 1 0 |ADELED:43|:310
- 5 - D 09 OR2 0 4 0 1 |ADELED:43|:325
- 1 - D 09 OR2 0 3 0 1 |ADELED:43|:334
- 3 - D 11 OR2 0 4 0 1 |ADELED:43|:351
- 3 - D 14 OR2 0 4 1 0 |ADELED:43|:358
- 8 - D 16 OR2 0 4 0 1 |ADELED:43|:384
- 5 - D 16 OR2 0 4 0 1 |ADELED:43|:388
- 6 - D 12 AND2 0 4 0 1 |ADELED:43|:402
- 5 - D 12 OR2 0 4 1 0 |ADELED:43|:406
- 3 - D 09 OR2 s 0 4 0 1 |ADELED:43|~430~1
- 7 - D 11 AND2 s 0 2 0 1 |ADELED:43|~430~2
- 1 - D 11 OR2 0 4 0 1 |ADELED:43|:442
- 2 - D 12 OR2 0 4 1 0 |ADELED:43|:454
- 4 - D 09 OR2 0 4 1 0 |ADELED:43|:504
- 2 - E 12 DFFE 0 2 0 3 |BINBCD:18|divide:U1|DFFQuotient1_0
- 1 - A 14 DFFE 0 5 0 3 |BINBCD:18|divide:U1|DFFQuotient1_1
- 8 - A 03 DFFE 0 5 0 3 |BINBCD:18|divide:U1|DFFQuotient1_2
- 8 - A 18 DFFE 0 5 0 3 |BINBCD:18|divide:U1|DFFQuotient1_3
- 1 - E 12 DFFE 0 2 0 2 |BINBCD:18|divide:U1|DFFStage1_0
- 1 - A 26 DFFE 0 2 0 2 |BINBCD:18|divide:U1|DFFStage1_1
- 1 - A 32 DFFE 0 2 0 2 |BINBCD:18|divide:U1|DFFStage1_2
- 4 - E 06 DFFE 0 2 0 2 |BINBCD:18|divide:U1|DFFStage1_3
- 1 - A 34 DFFE 0 2 0 1 |BINBCD:18|divide:U1|DFFStage1_4
- 1 - A 28 DFFE 0 2 0 1 |BINBCD:18|divide:U1|DFFStage1_5
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